VHDL IP核乘法器及仿真

top.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;



entity top is
port (
    clk: IN std_logic;
    a: IN std_logic_VECTOR(15 downto 0);
    b: IN std_logic_VECTOR(15 downto 0);
 q: OUT std_logic_VECTOR(31 downto 0);
    p: OUT std_logic_VECTOR(31 downto 0));
end top;

architecture Behavioral of top is
component mult
    port (
    clk: IN std_logic;
    a: IN std_logic_VECTOR(15 downto 0);
    b: IN std_logic_VECTOR(15 downto 0);
    p: OUT std_logic_VECTOR(31 downto 0));
end component;
component xiangcheng
port(
a : in  STD_LOGIC_VECTOR (15 downto 0);
           b : in  STD_LOGIC_VECTOR (15 downto 0);
           q : out  STD_LOGIC_VECTOR (31 downto 0));