library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity top is
port(
clk:in std_logic;
rst:in std_logic;
counter:out std_logic_vector(3 downto 0)
);
end top;
architecture Behavioral of top is
signal counter_tmp:std_logic_vector(3 downto 0);
begin
counter<=counter_tmp;
process(clk,rst)
begin
if(rst='0') then
counter_tmp<="0000";
elsif rising_edge(clk) then
counter_tmp<=counter_tmp+1;
if(counter_tmp="1100") then
counter_tmp<="0001";
end if;
end if;
end process;
end Behavioral;
本内容试读结束,登录后可阅读更多
下载后可阅读完整内容,剩余1页未读,立即下载