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JESD21-C目录

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JEDEC Standard No. 21C

CONFIGURATIONS FOR SOLID STATE MEMORIES

Contents

Section Title Release #............. Page #

1 Background ..................................................................................................... 1 ..........................1-1

2 Terms and Definitions .................................................................................... 1 ..........................2-1

2.1 Conventional Device Pin Names....................................................................... 9.10 .....................2-2

2.2 Multiport DRAM Pin Names .............................................................................. 3 ..........................2-5

2.3 Power Pin Names ............................................................................................. 9 ..........................2-6

2.4 Device Type Names.......................................................................................... 9.11 .....................2-7

2.5 Miscellaneous Device Related Terms............................................................... 1 ..........................2-9

2.6 Special Operational Cycles for MPDRAM......................................................... 1 ........................2-10

2.7 Package-Related Terms ................................................................................... 5 ........................2-12

2.8 Memory Card Pin Names.................................................................................. 3 ........................2-13

2.9 SRAM and SSRAM Special Pin Names............................................................ 6.11 ...................2-14

2.10 SLDRAM Special Pin Names............................................................................ 9 ........................2-15

2.11 MCP Signal Names........................................................................................... 19r20.................2-17

3 Memory Device Standards ............................................................................. 1 ..........................3-1

3.1 General Standards ............................................................................................ 1 .......................3.1-1

3.1.1 Byte Wide.......................................................................................................... 1 .......................3.1-1

3.1.1.1 32K to 256K by 8 A/A MX Family in DIP ........................................................... 1 .......................3.1-1

3.2 Read Only Memory (ROM).............................................................................. 1 .......................3.2-1

3.2.0 ROM General Standards................................................................................... 5 .......................3.2-2

3.2.0.1 Mask ROM Fast Address Mode Definition ........................................................ 5 .......................3.2-2

3.2.1 ROM, Byte Wide ............................................................................................... 1 ....................3.2.1-1

3.2.1.1 2K to 8K by 8 ROM Family in DIP, Type A ....................................................... 1 ....................3.2.1-1

3.2.1.2 4K by 8 ROM in DIP, Type B ............................................................................ 1 ....................3.2.1-1

3.2.1.3 8K to 128K by 8 ROM Family in DIP................................................................. 1 ....................3.2.1-1

3.2.1.4 2K to 32K by 8 ROM Family in RCC................................................................. 1 ....................3.2.1-1

3.2.1.5 32K to 512K by 8 ROM Family in SOJ.............................................................. 1 ....................3.2.1-1

3.2.1.6 128K to 1M by 8 ROM in DIP............................................................................ 1 ....................3.2.1-1

3.2.1.7 64K to 512K by 9 ROM in DIP .......................................................................... 1 ....................3.2.1-1

3.2.1.8 2 to 64 X 16K by 8 Page Select ROM in DIP .................................................... 1 ....................3.2.1-1

3.2.1.9 512K and 1M by 8 ROM in QFP ....................................................................... 2 ....................3.2.1-1

3.2.2 ROM, Word Wide.............................................................................................. 1 ....................3.2.2-1

3.2.2.1 32K to 256K by 16 ROM in DIP ........................................................................ 1 ....................3.2.2-3

3.2.2.2

32K to 256K by 16 ROM in SCC....................................................................... 1 ....................3.2.2-3

3.2.2.3 16K to 256K by 16 Address/Data MX ROM in DIP .......................................... 1 ....................3.2.2-3

3.2.2.4 16K to 256K by 16 Address/Data MX ROM in RCC ........................................ 1 ....................3.2.2-3

3.2.2.5 256K and 512K by 16 ROM in QFP .................................................................. 2 ....................3.2.2-3

3.2.2.6 512K to 128M by 16 ROM in DIP and SOP ..................................................... 6 ....................3.2.2-3

3.2.2.7 512K and 1M by 16 ROM in SCC ..................................................................... 3 ....................3.2.2-3

3.3 Programmable Read Only Memory (PROM) .................................................... 1 .......................3.3-1

3.3.1 PROM, Nibble Wide .......................................................................................... 1 ....................3.3.1-1

3.3.1.1 25K and .5K by 4 TTL PROM in DIP................................................................. 1 ....................3.3.1-3

3.3.1.2 25K by 4 ECL PROM in DIP ............................................................................. 1 ....................3.3.1-3

JEDED Standard No. 21C

3.3.1.3 1K and 2K by 4 TTL PROM in DIP....................................................................1 ................... 3.3.1-3

3.3.1.4 1K and 2K by 4 TTL PROM in SOP ..................................................................1 ................... 3.3.1-3

3.3.1.5 4K to 8K by 4 TTL PROM in DIP.......................................................................2 ................... 3.3.1-3

3.3.1.6 25K to 2K by 4 TTL PROM Family in RCC ......................................................1 ................... 3.3.1-3

3.3.1.7 4K by 4 TTL PROM, 4K by 4 TTL RPROM in SCC...........................................1 ................... 3.3.1-3

3.3.1.8 1K to 8K TTL by 4 PROM Family in RCC .........................................................1 ................... 3.3.1-3

3.3.1.9 1K to 8K TTL by 4 PROM Family in SCC..........................................................1 ................... 3.3.1-3

3.3.1.10 1K to 4K by 4 DPROM Families in DIP and SCC..............................................1 ................... 3.3.1-4

3.3.1.11 1K to 16K by 4 ECL PROM Family in DIP ........................................................1 ................... 3.3.1-4

3.3.2 PROM, Byte Wide .............................................................................................1 ................... 3.3.2-1

3.3.2.1 32 by 8 TTL PROM in DIP and SCC .................................................................1 ................... 3.3.2-3

3.3.2.2 32 by 8 ECL PROM in DIP and SCC ................................................................1 ................... 3.3.2-3

3.3.2.3 25K and .5K by 8 TTL PROM in DIP and SCC ................................................1 ................... 3.3.2-3

3.3.2.4 25K to 8K by 8 TTL PROM Family in DIP ........................................................1 ................... 3.3.2-3

3.3.2.5 5K to 4K by 8 TTL LPROM Family in DIP ........................................................1 ................... 3.3.2-3

3.3.2.6 5K to 4K by 8 TTL RPROM Family in DIP ........................................................1 ................... 3.3.2-3

3.3.2.7 5K to 8K by 8 TTL PROM FAMILIES in RCC and SCC ...................................1 ................... 3.3.2-3

3.3.2.8 5K to 2K by 8 TTL RPROM Family in SCC ......................................................1 ................... 3.3.2-4

3.3.2.9 16K to 64K by 8 TTL PROM Family in DIP ......................................................1 ................... 3.3.2-4

3.3.2.10 512 by 8 ECL RPROM in DIP and SCC............................................................2 ................... 3.3.2-4

3.3.3 PROM, Word Wide............................................................................................1 ................... 3.3.3-1

3.3.3.1 32 and 64 by 16 PROM in DIP and SCC .........................................................1 ................... 3.3.3-3

3.3.4 PROM Package Conversion .............................................................................1 ................... 3.3.4-1

3.3.4.1 PROM DIP to SO Conversion, 16, 18, 20, 24 DIP ............................................1 ................... 3.3.4-1

3.4 Erasable Programmable Read Only Memory (EPROM) ..............................1 ...................... 3.4-1

3.4.1 EPROM, Byte Wide...........................................................................................1 ................... 3.4.1-1

3.4.1.1 4K by 8 EPROM in DIP, Type A........................................................................1 ................... 3.4.1-3

3.4.1.2 4K and 8K by 8 EPROM in DIP.........................................................................1 ................... 3.4.1-3

3.4.1.3 8K to 64K by 8 EPROM Family in DIP ..............................................................1 ................... 3.4.1-3

3.4.1.4 2K to 512K by 8 EPROM Family in RCC .........................................................1 ................... 3.4.1-3

3.4.1.5 32K to 512K by 8 EPROM Family in SOJ .........................................................1 ................... 3.4.1-3

3.4.1.6 128K to 1M by 8 EPROM Family in DIP............................................................1 ................... 3.4.1-3

3.4.1.7 64K to 512K by 9 EPROM Family in DIP ..........................................................1 ................... 3.4.1-3

3.4.1.8 2 to 64 X 16K by 8 PAGE SELECT EPROM Family in DIP ..............................1 ................... 3.4.1-3

3.4.1.9 128K to 512K by 8 EPROM Family in TSOP1 ..................................................4 ................... 3.4.1-3

3.4.2 EPROM, Word Wide .........................................................................................1 ................... 3.4.2-1

3.4.2.1 32K to 256K by 16 EPROM in DIP....................................................................1 ................... 3.4.2-3

3.4.2.2 32K to 256K by 16 EPROM in SCC ..................................................................1 ................... 3.4.2-3

3.4.2.3 16K to 256K by 16 Address/Data MX EPROM in DIP ......................................1 ................... 3.4.2-3

3.4.2.4 16K to 256K by 16 Address/Data MX EPROM in RCC ....................................1 ................... 3.4.2-3

3.4.2.5 512K to 128M by 16 EPROM or OTP in DIP and SOP ....................................6 ................... 3.4.2-3

3.4.2.6 512K and 1M by 16 EPROM in SCC.................................................................3 ................... 3.4.2-3

3.4.2.7 64K to 256K by 16 EPROM in TSOP1 .............................................................4 ................... 3.4.2-3

3.5 Electrically Erasable Programmable Read Only Memory, EEPROM ..............................1 ...................... 3.5-1

3.5.1 EEPROM, Byte Wide ........................................................................................1 ................... 3.

5.1-1

3.5.1.1 5K to 2K by 8 EEPROM Family in DIP .............................................................1 ................... 3.5.1-2

Contents (Cont’d)

Section Title Release # Page #

JEDEC Standard No. 21C

iii

3.5.1.2 2K and 4K by 8 EEPROM in RCC .................................................................... 1....................3.5.1-2

3.5.1.3 1K to 32K by 8 EEPROM Family in DIP .......................................................... 1....................3.5.1-2

3.5.1.4 5K to 32K by 8 EEPROM Family in RCC ......................................................... 1....................3.5.1-2

3.5.1.5 32K to 256K by 8 EEPROM Family in SOJ ...................................................... 1....................3.5.1-2

3.5.1.6 32K to 512K by 8 EEPROM Family in DIP ....................................................... 1....................3.5.1-2

3.5.1.7 32K to 256K by 8 EEPROM Family in RCC...................................................... 1....................3.5.1-2

3.5.1.8 32K to 256K by 9 EEPROM Family in DIP ....................................................... 1....................3.5.1-2

3.5.1.9 128K to 1M by 8 EEPROM Family in SCC ....................................................... 1....................3.5.1-2

3.5.1.10 32K to 256K by 8 EEPROM Family in TSOP1 ................................................. 2 ....................3.5.1-3

3.5.1.11 Extended Feature Set for 256K Bit EEPROM .................................................. 2....................3.5.1-3

3.5.1.12 Optional Command Set for Dual-Supply EEPROM .......................................... 3....................3.5.1-3

3.5.1.13 512K by 8 Dual-Supply EEPROM in RCC ....................................................... 5....................3.5.1-3

3.5.1.14 128K to 512K by 8 Single-Supply EEPROM Family in

DIP RCC and TSOP1 ...................................................................................... 5 ....................3.5.1-3

3.5.1.15 256K to 512K and 1M by 8 Dual-Supply EEPROM in TSOP1.......................... 6....................3.5.1-4

3.5.1.16 1M to 8M by 8 Single-Supply EEPROM Family in TSOP1 .............................. 5....................3.5.1-4

3.5.1.17 8K by 256B or 264B SERIAL ACCESS EEPROM in TSOP2 .......................... 6....................3.5.1-4

3.5.1.18 1M, 2M BU 8 Single- or Dual-Supply EEPROM in PSOP2............................... 7....................3.5.1-4

3.5.1.19 4Mb to 32Mb Density by 8 Dual Supply Flash EEPROM

in 8 X 5 GRID Micro BGA Package ................................................................. 9....................3.5.1-4

3.5.1.20 2K Bit Serial, Single-Supply EEPROM in 8 Pin SOG ....................................... 9....................3.5.1-4

3.5.1.21 2-WIRE EEPROM in Small Footprint Package ................................................ 14..................3.5.1-4

3.5.2 EEPROM, Word Wide....................................................................................... 1....................3.5.2-1

3.5.2.1 4K to 32K by 16 EEPROM in DIP ..................................................................... 1....................3.5.2-2

3.5.2.2 4K to 256K by 16 EEPROM in SCC ................................................................. 1....................3.5.2-2

3.5.2.3 256K to 128M by 16 EEPROM in DIP and SOG ............................................. 6....................3.5.2-2

3.5.2.4 1M to 4M by 16 DS EEPROM in SSOP ........................................................... 6....................3.5.2-2

3.5.2.5 1M to 4M Density, by 8 or 16 FEEPROM in PSOP .......................................... 7....................3.5.2-2

3.5.2.6 1M to 32M Density, by 8 or 16 FEEPROM in TSOP1....................................... 7....................3.5.2-2

3.5.2.7 4Mb to 32Mb Density by 8 and 16 Dual Supply Flash

EEPROM in 8 X 6 GRID Micro BGA Package ................................................. 9....................3.5.2-2

3.5.2.8 16Mb to 64Mb Density by 8 and 16, Dual supply Flash

EEPROM in 8 X 9 GRID Micro BGA Package ................................................. 9....................3.5.2-3

3.5.2.9 8Mb to 128Mb Density FEEPROM/SRAM in BGA .......................................... 10..................3.5.2-3

3.5.2.10 4M to 64M by 16 FEEPROM in TSOP1 ........................................................... 11..................3.5.2-3

3.5.2.11 2M to 64M by 16 FEEPROM in FBGA ............................................................. 11..................3.5.2-3

3.5.2.12 4M to 8M and 16M by 16 FEEPROM with SDRAM Interface .......................... 11..................3.5.2-3

3.5.2.13 128Mb to 4Gb Density FEEPROM, User Selectable as X8

or X16 in SSOP ............................................................................................... 11..................3.5.2-4

3.5.2.14 Single-Supply 16Mb and 32Mb (x16/x32) FEEPROM

in 80-Pin PQFP ................................................................................................ 12..................3.5.2-4

3.5.2.15 128Mb TO1Gb(x8/x16) FEEPROM in 64-Ball LBGA ....................................... 14..................3.5.2-4

3.5.2.16

28Mb to 1Gb (x8/x16) FEEPROM in 64-Ball LBGA ......................................... 14..................3.5.2-4

3.5.2.17 16Mb to 512Mb (x8/x16) FEEPROM in 52-Pin TSOP2 ................................... 14..................3.5.2-4

3.5.2.18 16Mb to 512Mb (x16) Synchronous 1.8V/3.0V FEEPROM

in 56-Pin TSOP1 .............................................................................................. 16..................3.5.2-5

3.5.2.19 16Mb to 1Gb (x16) Synchronous 1.8V/3.0 VFEEPROM

in 64-Ball LFBGA ............................................................................................. 16..................3.5.2-5

3.5.3 EEPROM Extended FEATURES ...................................................................... 1....................3.5.3-1

Contents (Cont’d)

Section Title Release # Page #

JEDED Standard No. 21C

3.5.3.1 Extended Feature Set for 256Kb EEPROM .....................................................1 ................... 3.5.3-3

3.5.3.2 Dual-Supply EEPROM Command Set .............................................................7 ................. 3.5.3-13

3.5.3.3 Single-Supply EEPROM Command Codes ......................................................7 ................. 3.5.3-14

3.5.3.4 EEPROM Toggle Bit Feature ............................................................................7 ................. 3.5.3-15

3.5.3.5 Synchronous DRAM Interface EEPROM (Flash) in 86-Pin TSOP2

and 90-Ball FBGA ............................................................................................12 ............... 3.5.3-16

3.5.3.6 EEPROM with Two SPD Software Write Protect Methods ..............................14 ............... 3.5.3-19

3.6 Nonvolatile Random Access Memory (NVRAM)...........................................1 ...................... 3.6-1

3.6.1 NVRAM , Nibble Wide .......................................................................................1 ...................... 3.6-3

3.6.1.1 25K and 1K by 4 NVRAM in DIP .......................................................................1 ...................... 3.6-3

3.6.2 NVRAM , Byte Wide ..........................................................................................1 ...................... 3.6-3

3.6.2.1 5K, 1K by 8 NVRAM in DIP ...............................................................................1 ...................... 3.6-3

3.6.2.2 5K and 1K by 8 NVRAM in RCC .......................................................................1 ...................... 3.6-3

3.6.2.3 5K to 16K by 8 NVRAM Family in DIP .............................................................1 ...................... 3.6-3

3.6.2.4 5K to 16K by 8 NVRAM Family in RCC ............................................................1 ...................... 3.6-3

3.6.2.5 32K to 256K by 8 NVRAM Family in SOJ .........................................................1 ...................... 3.6-3

3.6.2.6 32K to 256K by 8 NVRAM Family in DIP ..........................................................1 ...................... 3.6-3

3.6.2.7 16K to 128K by 9 NVRAM Family in DIP ..........................................................1 ...................... 3.6-3

3.6.3 LPDDR NVRAM ................................................................................................18 ................. 3.6.3-1

3.7 Static Random Access Memory (SRAM).......................................................1 ...................... 3.7-1

3.7.1 JTAG Extension to Revolutionary Pinout SRAM Devices ................................4 ...................... 3.7-1

3.7.1 Bit Wide TTL SRAM ..........................................................................................1 ................... 3.7.1-1

3.7.1.1 25K and 1K by 1 TTL SRAM in DIP ..................................................................1 ................... 3.7.1-3

3.7.1.2 25K and 1K by 1 TTL SRAM in SCC.................................................................1 ................... 3.7.1-3

3.7.1.3 4K to 2M by 1 TTL SRAM Family in DIP ..........................................................1 ................... 3.7.1-3

3.7.1.4 16K by 1 TTL SRAM in RCC.............................................................................1 ................... 3.7.1-3

3.7.1.5 64K by 1 TTL SRAM in RCC.............................................................................1 ................... 3.7.1-3

3.7.1.6 16K to 2M by 1 TTL SRAM in SOJ....................................................................5 ................... 3.7.1-3

3.7.1.7 256K to 16M by 1 TTL SRAM and 4M by 1 SSRAM in DIP, SOJ,

and TSOP2 .......................................................................................................4 ................... 3.7.1-3

3.7.1.8 256K by 1 TTL SRAM in RCC...........................................................................1 ................... 3.7.1-3

3.7.1.9 4M and 16M SRAMConfigurable to X1 or X4 in DIP, SOJ,

and TSOP2 .......................................................................................................4 ................... 3.7.1-3

3.7.2 Bit Wide ECL SRAM..........................................................................................1 ................... 3.7.2-1

3.7.2.1 1K to 256K by 1 ECL SRAM Family in DIP ......................................................1 ................... 3.7.2-3

3.7.2.2 256K to 16M by 1 ECL SRAM and 4M by 1 SSRAM in DIP, SOJ,

and TSOP2 .......................................................................................................4 ................... 3.7.2-3

3.7.2.3 64K and 256K by 1 ECL SRAM in FLATPACK ................................................2 ................... 3.7.2-3

3.7.2.4 256K to 16M by 1 ECL SSRAM Family in DIP, SOJ, and TSOP2 ....................4 ................... 3.7.2-3

3.7.3 Nibble Wide TTL SRAM ....................................................................................1 ................... 3.7.3-1

3.7.3.1 16 by 4, Inverting and Noniverting TTL SRAM in DIP and SCC .......................1 ................... 3.7.3-3

3.7.3.2 25K by 4 TTL SRAM in DIP and RCC...............................................................1 ................... 3.7.3-3

3.7.3.3 256 by 4 TTL SRAM with G in SCC ..................................................................1 ................... 3.7.3-3

3.7.3.4 4K to 64K by 4 TTL SRAM without G Family in DIP ........................................1 ................... 3.7.3-3

3.7.3.5 4K by 4 TTL SRAM in RCC...............................................................................1 ................... 3.7.3-3

3.7.3.6 4K to 1M by 4 TTL SRAM with G Family in DIP................................................1 ................... 3.7.3-3

3.7.3.7 16K to 256K by 4 TTL SRAM with and without G Family in RCC ....................1 ................... 3.7.3-3

3.7.3.8 16K and 64K by 4 TTL SRAM in RCC ..............................................................1 ................... 3.7.3-3

Contents (Cont’d)

Section Title Release # Page #

JEDEC Standard No. 21C

3.7.3.9 4K to 1M by 4 TTL SRAM with and without G Family in SOJ,

and TSOP2 ...................................................................................................... 5....................3.7.3-4

3.7.3.10 64K to 4M by 4 TTL SRAM in DIP, SOJ, and TSOP2 ..................................... 4....................3.7.3-4

3.7.3.11 64K to 4M by 4 TTL SRAM with Separate Data I/O in DIP, SOJ,

and TSOP2 ...................................................................................................... 4....................3.7.3-4

3.7.3.12 64K to 4M by 4 Synchronous SRAM (SSRAM) in DIP, SOJ,

and TSOP2 ...................................................................................................... 4....................3.7.3-4

3.7.3.13 4K and 16K by 4 CACHE TAG SRAM in DIP and SOJ ................................... 1....................3.7.3-4

3.7.3.14 4M and 16M SRAM, Configurable to X1 or X4 in DIP and SOJ ....................... 1....................3.7.3-4

3.7.4 Nibble Wide ECL SRAM ................................................................................... 1 ....................3.7.4-1

3.7.4.1 25K and 1K by 4, 100K ECL SRAM in DIP and SFP ....................................... 1....................3.7.4-3

3.7.4.2 1K to 16K by 4, 10K and 100K ECL SRAM in DIP .......................................... 1....................3.7.4-3

3.7.4.3 25K to 16K by 4, 10K and 100K ECL SRAM Family in DIP ............................. 1....................3.7.4-3

3.7.4.4 16K by 4,10K and 100K ECL SSRAM in DIP .................................................. 1....................3.7.4-3

3.7.4.5 64K to 4M by 4 ECL SRAM in DIP, SOJ, and TSOP2 ..................................... 4 ....................3.7.4-3

3.7.4.6 64K to 4M by 4 ECL SRAM with Separate Data I/O in DIP, SOJ,

and TSOP2 ...................................................................................................... 4....................3.7.4-3

3.7.4.7 64K to 4M by 4 ECL Synchronous SRAM (SSRAM) in DIP, SOJ,

and TSOP2 ...................................................................................................... 4....................3.7.4-4

3.7.4.8 64K by 4 ECL SRAM in FP ............................................................................... 2 ....................3.7.4-4

3.7.4.9 256K by 4/512K by 2 Reconfigurable SRAM in DIP and SOJ .......................... 2....................3.7.4-4

3.7.4.10 64K to 4M by 4 SRAM Family in DIP and SOJ in DIP, SOJ,

and TSOP2 ...................................................................................................... 4....................3.7.4-4

3.7.4.11 64K to 4M by 4 SSRAM Family in SIP and SOJ in DIP, SOJ,

and TSOP2 ...................................................................................................... 4....................3.7.4-4

3.7.4.12 64K to 4M by 4 SSRAM Family in SIP and SOJ in DIP, SOJ,

and TSOP2 ...................................................................................................... 4....................3.7.4-4

3.7.5 Byte Wide TTL SRAM....................................................................................... 1....................3.7.5-1

3.7.5.1 64 by 9 TTL SRAM in SCC ............................................................................... 1....................3.7.5-3

3.7.5.2 1K and 2K by 8 TTL SRAM in DIP.................................................................... 1....................3.7.5-3

3.7.5.3 2K and 4K by 8 TTL SRAM in RCC .................................................................. 1....................3.7.5-3

3.7.5.4 2K to 32K by 8 TTL SRAM Family in DIP and SOJ .......................................... 1....................3.7.5-3

3.7.5.5 5K to 32K by 8 TTL SRAM Family in RCC ...................................................... 1....................3.7.5-3

3.7.5.6 32K to 512K by 8 TTL SRAM Family in SOJ or TSOP2 ................................... 4....................3.7.5-3

3.7.5.7 64K to 512K by 8 TTL SRAM Family in DIP ..................................................... 1....................3.7.5-3

3.7.5.8 32K to 256K by 9 TTL SRAM Family in DIP ..................................................... 1....................3.7.5-3

3.7.5.9 32K to 2M by 8 and 512K to 2M by 9 TTL SRAM in DIP, SOJ,

and TSOP2 ...................................................................................................... 4..............

......3.7.5-3

3.7.5.10 32K and 128K by 8 TTL SSRAM in DIP and SOJ ........................................... 1....................3.7.5-3

3.7.5.11 2K to 32K by 9 DPSRAM Family in 68 SCC .................................................... 1 ....................3.7.5-3

3.7.5.12 32K by 9 CACHE SRAM in 44 SCC ................................................................. 2....................3.7.5-3

3.7.5.13 128K by 8 SRAM in TSOP1.............................................................................. 2....................3.7.5-3

3.7.5.14 128K by 8 and 9 SSRAM in SOJ ...................................................................... 2 ....................3.7.5-3

3.7.5.15 1K and 2K by 8 DPSRAM Family in 48 DIP...................................................... 2....................3.7.5-3

3.7.5.16 128K to 512K by 8 SRAM Family in 32 CDSO-N ............................................. 3....................3.7.5-3

3.7.5.17 128K to 512K by 8 and 9 SSRAM and 128K by 9 SRAM in 33 DIP

and SOJ ........................................................................................................... 3....................3.7.5-4

3.7.5.18 128K to 2M by 8/9 Burst SRAM in BGA ........................................................... 5....................3.7.5-4

3.7.5.19 128K to 2M by 8/9 SSRAM in BGA................................................................... 5....................3.7.5-4

3.7.5.20 32K by 8 SRAM in TSOP1................................................................................ 7 ....................3.7.5-4

Contents (Cont’d)

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JESD21-C: Table of Contents（目录表）

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JESD21-C: Table of Contents（目录表）

【最新版可复制文字】 JEDEC 21C.pdf

JEDEC工业标准目录(部分).doc

Memory Configurations JESD21-C JEDEC Standards

jesd212c JEDEC标准规范，GDDR5

JESD22简介目录

DDR3 JEDEC 官方标准文档

JEDEC标准族

JESD79-4C：DDR4 SDRAM Standard(DDR4标准)-最新完整版-带详细书签(265页)

JEDEC JESD79-3-3：2013 Addendum No. 3 to JESD79-3：3D Stacked SDRA

【最新版可复制文字】 JESD209-5B：2021 Low Power Double Data Rate

JESD79-4C：2020 DDR4 SDRAM Standard

UFS V2.1-JESD220C

JEDEC standard No.21, DDR3 DIMM design spec

JESD209-5A：2020 Low Power Double Data Rate 5(LPDDR5) - 完整英文电子版（5

JESD402-1：2020 Temperature Grade and Measurement Specifications

JEDEC JESD22-B130：2022 建立 DRAM 器件 X 射线总剂量限值的测试方法 - 完整英文电子版（15页）

JEDEC JESD300-5：2020 SPD5118, SPD5108 Hub and DDR5 Serial Presen

JEDEC JESD304-4.01：2021 DDR4 NVDIMM-P Bus Protocol -最新完整英文电子版（223页）.pdf

JESD79-4C：2020 DDR4 SDRAM Standard(DDR4标准）-最新完整英文电子版（262页）.zip

JEDEC JESD214-01：2017 Constant-Temperature Aging Method to Chara

JEDEC JESD402-1：2020 Temperature Grade and Measurement Specifica

JEDEC JESD50B-01：2008 Special Requirements for Maverick Product

JESD209-4D, LPDDR4 JEDEC SPEC, June 1, 2021 最新版本。

JESD84-A43：2007 Embedded MultiMediaCard (eMMC) eMMC-Card Product

JEDEC JESD89-2B：2021 Test Method for Alpha Source Accelerated So

JESD84-A42：2007 Embedded MultiMediaCard (eMMC) Product Standard,

JESD84-C01：2007 MultiMediaCard (MMC) Card Mechanical Standard -

串口助手工具合集.zip

OLED显示温度和时间-STM32F103C8T6（完整程序工程+原理图+相关资料）.zip

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