<html>
<head>
<title>Sample Waveforms for PLL_ctrl.v </title>
</head>
<body>
<h2><CENTER>Sample behavioral waveforms for design file PLL_ctrl.v </CENTER></h2>
<P>The following waveforms show the behavior of altpll megafunction for the chosen set of parameters in design PLL_ctrl.v. The design PLL_ctrl.v has Cyclone AUTO pll configured in NORMAL mode The primary clock input to the PLL is INCLK0, with clock period 40000 ps. Output port LOCKED will go high when the PLL locks to the input clock. </P>
<CENTER><img src=PLL_ctrl_wave0.jpg> </CENTER>
<P><CENTER><FONT size=2>Fig. 1 : Wave showing NORMAL mode operation. </CENTER></P>
<P><FONT size=3>When input port ARESET is asserted, it will cause the LOCKED port and all CLK outputs to drop to zero. The PLL will relock to the input clock when this port is deasserted. </P>
<P></P>
</body>
</html>
FPGA读写SDRAM实验源码
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2012-05-09
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SDRAM_Test.zip （70个子文件） 
SDRAM_Test 
datagene.v 4KB stp1.stp 204KB sdr_test.map.summary 481B sdr_test.sta.summary 4KB uart_tx.v 2KB rdfifo.bsf 3KB sdr_test.cdf 333B sdfifo_ctrl.v 3KB PLL_ctrl.cnxerr 208B wrfifo.v 7KB PLL_ctrl.cnx 9KB sdr_test.pin 26KB sdr_test.sof 235KB wrfifo_bb.v 6KB sdr_test.fit.smsg 513B sdr_test.jdi 4KB PLL_ctrl.qip 542B sdr_test_assignment_defaults.qdf 41KB clk_ctrl_bb.v 14KB PLL_ctrl.bsf 4KB clk_ctrl_inst.v 162B wrfifo.bsf 3KB sdram_top.v 3KB sdr_test.v 5KB wrfifo_inst.v 188B
rdfifo_waveforms.html 753B sdram_ctrl.v 12KB sdr_test.qsf 27KB PLL_ctrl_bb.v 13KB sdram_cmd.v 5KB wrfifo.qip 446B PLL_ctrl.v 17KB wrfifo_waveforms.html 753B sdr_para.v 3KB PLL_ctrl.ppf 614B rdfifo_inst.v 188B rdfifo.v 7KB sdr_test.done 26B clk_ctrl.ppf 617B sys_ctrl.v 2KB sdr_test.sdc 20KB PLL_ctrl_inst.v 162B sdr_test.qpf 907B 调式记录 
process1.jpg 123KB work_state_r.jpg 100KB init_state_r.jpg 70KB sdfifo_ctrl_uut_sdffifoctrl.jpg 51KB process2.jpg 123KB
rdack_2_9.bmp 1.91MB rdfifo_wave0.jpg 96KB 1.jpg 441KB PLL_ctrl_wave0.jpg 782KB read_process.jpg 75KB write_process.jpg 77KB process3.jpg 122KB sdram_top_uut_sdramtop.jpg 71KB wrfifo_wave0.jpg 96KB rdack_0_7.bmp 1.91MB sdr_test.jpg 101KB rdfifo.qip 445B clk_ctrl.v 18KB rdfifo_bb.v 6KB PLL_ctrl_waveforms.html 862B sdr_test.qws 532B sdr_test.fit.summary 623B sdram_wr_data.v 3KB clk_ctrl.qip 456B uart_speed_select.v 2KB write_read.tbl 238KB uart_ctrl.v 1KB
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