1、简单 4 位计数器程序：
module count4(clk,cnt);
input clk;
output reg[3:0]cnt=4'b0;
always @(posedge clk)
begin
cnt<=cnt+1;
end
endmodule
测试程序：
`timescale 1 ns/10 ps
module test_count4();
reg clk=0;
wire [3:0]cnt;
count4 i1(.clk(clk),.cnt(cnt));
always #10 clk=~clk;
initial
begin
$monitor($time,,,"clk=%d cnt=%d",clk,cnt);
#400 $stop;
end
endmodule
仿真波形：
2、异步清零 4 位计数器源程序
module count4_reset(clk,rst,cnt);
input clk,rst;
output reg[3:0]cnt=4'b0;
always @(posedge clk or negedge rst)
begin
if(!rst) cnt<=4'b0;
else cnt<=cnt+1;
end
endmodule
测试程序
`timescale 1 ns/10 ps
module test_count4_reset();
