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### GOOGLE的TPU论文知识点解析 #### 一、概述 Google公开了其内部设计与使用的Tensor Processing Unit（简称TPU）的相关技术细节。该论文详细介绍了TPU的设计理念、架构特性以及在数据中心内的实际表现。TPU作为一种专门针对神经网络（Neural Networks, NN）推理阶段加速的定制化ASIC芯片，旨在提升成本效率与能耗比。 #### 二、TPU的背景与设计理念随着深度学习领域的快速发展，传统CPU和GPU在处理大规模神经网络计算时面临着能效瓶颈。为了解决这一问题，Google设计并部署了TPU。该论文强调，许多架构师认为，在特定领域内进行硬件优化是实现成本-能量-性能重大突破的关键途径之一。TPU正是基于这一理念而诞生的。 #### 三、TPU的核心架构 TPU的核心是一块拥有65,536个8位乘法累加单元（MAC）的矩阵乘法单元，峰值吞吐量可达92万亿次操作每秒（TOPS）。此外，TPU还配备有28MB的软件管理的片上内存。这种设计能够显著提高神经网络推理任务的执行效率。 #### 四、TPU的特点 1. **确定性执行模型**：TPU采用了确定性的执行模型，这与CPU和GPU中的时间变化优化策略（如缓存、乱序执行、多线程等）不同。这种确定性的执行方式更符合神经网络应用对99%响应时间的要求。 2. **低功耗与小型化**：尽管TPU具有大量的MAC单元和较大的内存，但它的整体尺寸相对较小，功耗较低。这是因为TPU省去了许多传统处理器中用于提高平均吞吐量而不是确保最低延迟的功能，如缓存、乱序执行等。 #### 五、TPU的实际应用效果 1. **性能提升**：根据论文提供的数据，TPU相较于同时期的高端GPU和CPU，在神经网络推理任务上的性能显著提高。 2. **能效比**：TPU不仅提高了性能，还极大地提升了能效比，这对于大规模数据中心来说尤为重要。 3. **成本效益**：由于TPU的低功耗特性，它在长期运行中的成本效益更高，尤其是在面对大量并行计算需求的情况下。 #### 六、总结通过公开TPU的设计原理和技术细节，Google展示了其在神经网络计算加速领域的技术创新能力。TPU的设计充分考虑了神经网络应用的特点，并通过一系列硬件优化措施实现了高性能、高能效和低成本的目标。未来，随着深度学习技术的发展，类似TPU这样的专用硬件将扮演越来越重要的角色。 #### 七、扩展阅读与研究方向对于希望深入了解TPU及其背后技术的读者，可以进一步探索以下几个方面： - TPU的具体硬件实现细节及其与现有处理器架构的比较。 - TPU在不同神经网络模型上的实际表现，包括训练阶段的表现。 - TPU与其他领域专用加速器（如FPGA、DSP等）之间的性能对比。 - 针对未来神经网络发展趋势，探讨TPU的可扩展性和灵活性改进方案。通过这些研究，不仅可以加深对TPU的理解，还能为未来的神经网络加速技术发展提供有价值的参考。

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In-Datacenter Performance Analysis of a Tensor Processing Unit

Norman P. Jouppi, Cliff Young, Nishant Patil, David Patterson, Gaurav Agrawal, Raminder Bajwa, Sarah Bates, Suresh

Bhatia, Nan Boden, Al Borchers, Rick Boyle, Pierre-luc Cantin, Clifford Chao, Chris Clark, Jeremy Coriell, Mike Daley,

Matt Dau, Jeffrey Dean, Ben Gelb, Tara Vazir Ghaemmaghami, Rajendra Gottipati, William Gulland, Robert Hagmann, C.

Richard Ho, Doug Hogberg, John Hu, Robert Hundt, Dan Hurt, Julian Ibarz, Aaron Jaffey, Alek Jaworski, Alexander Kaplan,

Harshit Khaitan, Andy Koch, Naveen Kumar, Steve Lacy, James Laudon, James Law, Diemthu Le, Chris Leary, Zhuyuan

Liu, Kyle Lucke, Alan Lundin, Gordon MacKean, Adriana Maggiore, Maire Mahony, Kieran Miller, Rahul Nagarajan, Ravi

Narayanaswami, Ray Ni, Kathy Nix, Thomas Norrie, Mark Omernick, Narayana Penukonda, Andy Phelps, Jonathan Ross,

Matt Ross, Amir Salek, Emad Samadiani, Chris Severn, Gregory Sizikov, Matthew Snelham, Jed Souter, Dan Steinberg,

Andy Swing, Mercedes Tan, Gregory Thorson, Bo Tian, Horia Toma, Erick Tuttle, Vijay Vasudevan, Richard Walter, Walter

Wang, Eric Wilcox, and Doe Hyun Yoon

Google, Inc., Mountain View, CA USA

Email: {jouppi, cliffy, nishantpatil, davidpatterson} @google.com

To appear at the 44th International Symposium on Computer Architecture (ISCA), Toronto, Canada, June 26, 2017.

Abstract

Many architects believe that major improvements in cost-energy-performance must now come from domain-specific

hardware. This paper evaluates a custom ASIC—called a Tensor Processing Unit (TPU)



— deployed in datacenters

since 2015 that accelerates the inference phase of neural networks (NN). The heart of the TPU is a 65,536 8-bit MAC

matrix multiply unit that offers a peak throughput of 92 TeraOps/second (TOPS) and a large (28 MiB)

software-managed on-chip memory. The TPU’s deterministic execution model is a better match to the 99th-percentile

response-time requirement of our NN applications than are the time-varying optimizations of CPUs and GPUs

(caches, out-of-order execution, multithreading, multiprocessing, prefetching, …) that help average throughput more

than guaranteed latency. The lack of such features helps explain why, despite having myriad MACs and a big

memory, the TPU is relatively small and low power. We compare the TPU to a server-class Intel Haswell CPU and an

Nvidia K80 GPU, which are contemporaries deployed in the same datacenters. Our workload, written in the high-level

TensorFlow framework, uses production NN applications (MLPs, CNNs, and LSTMs) that represent 95% of our

datacenters’ NN inference demand. Despite low utilization for some applications, the TPU is on average about 15X -

30X faster than its contemporary GPU or CPU, with TOPS/Watt about 30X - 80X higher. Moreover, using the GPU’s

GDDR5 memory in the TPU would triple achieved TOPS and raise TOPS/Watt to nearly 70X the GPU and 200X the

CPU.

Index terms–DNN, MLP, CNN, RNN, LSTM, neural network, domain-specific architecture, accelerator

1. Introduction to Neural Networks

The synergy between the large data sets in the cloud and the numerous computers that power it has enabled a renaissance in

machine learning. In particular, deep neural networks



(DNNs) have led to breakthroughs such as reducing word error rates in

speech recognition by 30% over traditional approaches, which was the biggest gain in 20 years [Dea16]; cutting the error rate

in an image recognition competition since 2011 from 26% to 3.5% [Kri12] [Sze15] [He16]; and beating a human champion at

Go [Sil16].

Neural networks (NN) target brain-like functionality and are based on a simple artificial neuron: a nonlinear function

(such as max(0, value)) of a weighted sum of the inputs. These artificial neurons are collected into layers, with the

outputs of one layer becoming the inputs of the next one in the sequence. The “deep” part of DNN comes from going beyond

a few layers, as the large data sets in the cloud allowed more accurate models to be built by using extra and larger layers to

capture higher levels of patterns or concepts, and GPUs provided enough computing to develop them.

The two phases of NN are called training



(or learning) and inference



(or prediction), and they refer to development

versus production. The developer chooses the number of layers and the type of NN, and training determines the weights.

Virtually all training today is in floating point, which is one reason GPUs have been so popular. A step called quantization

transforms floating-point numbers into narrow integers—often just 8 bits—which are usually good enough for inference.

Eight-bit integer multiplies can be 6X less energy and 6X less area than IEEE 754 16-bit floating-point multiplies, and the

advantage for integer addition is 13X in energy and 38X in area [Dal16].

Three kinds of NNs are popular today:

1. Multi-Layer Perceptrons



(MLP): Each new layer is nonlinear functions of weighted sum of all outputs (fully

connected



) from a prior one, which reuses the weights.

2. Convolutional Neural Networks



(CNN): Each ensuing layer is a set of of nonlinear functions of weighted sums of

spatially nearby subsets of outputs from the prior layer, which also reuses the weights.

3. Recurrent Neural Networks



(RNN): Each subsequent layer is a collection of nonlinear functions of weighted sums of

outputs and the previous state. The most popular RNN is Long Short-Term Memory



(LSTM). The art of the LSTM is

in deciding what to forget and what to pass on as state to the next layer. The weights are reused across time steps.

Table 1 shows two examples of each of the three types of NNs—which represent 95% of NN inference workload in our

datacenters—that we use as benchmarks. Typically written in TensorFlow [Aba16], they are surprisingly short: just 100 to

1500 lines of code. Our benchmarks are small pieces of larger applications that run on the host server, which can be thousands

to millions of lines of C++ code. The applications are typically user-facing, which leads to rigid response-time limits.

Each model needs between 5M and 100M weights (9th column of Table 1), which can take a lot of time and energy to

access. To amortize the access costs, the same weights are reused across a batch



of independent examples during inference or

training, which improves performance.

This paper describes and measures the Tensor Processing Unit



(TPU



) and compares its performance and power for

inference to its contemporary CPUs and GPUs. Here is a preview of the highlights:

● Inference apps usually emphasize response-time over throughput since they are often user-facing.

● As a result of latency limits, the K80 GPU is under-utilized for inference, and is just a little faster than the Haswell

CPU.

● Despite having a much smaller and lower power chip, the TPU has 25 times as many MACs and 3.5 times as much

on-chip memory as the K80 GPU.

● The TPU is about 15X - 30X faster at inference than the K80 GPU and the Haswell CPU.

● Four of the six NN apps are memory-bandwidth limited on the TPU; if the TPU were revised to have the same

memory system as the K80 GPU, it would be about 30X - 50X faster than the GPU and CPU.

● The performance/Watt of the TPU is 30X - 80X that of contemporary products; the revised TPU with K80 memory

would be 70X - 200X better.

● While most architects have been accelerating CNNs, they represent just 5% of our datacenter workload.

Name

LOC

Layers

Nonlinear

function

Weights

TPU Ops /

Weight Byte

TPU Batch

Size

% of Deployed

TPUs in July 2016

Conv

Vector

Pool

Total

MLP0

100

ReLU

20M

200

61%

MLP1

1000

ReLU

168

LSTM0

1000

sigmoid, tanh

52M

29%

LSTM1

1500

sigmoid, tanh

34M

CNN0

1000

ReLU

2888

CNN1

1000

ReLU

100M

1750

Table 1. Six NN applications (two per NN type) that represent 95% of the TPU’s workload. The columns are the NN name; the number of

lines of code; the types and number of layers in the NN (FC is fully connected, Conv is convolution, Vector is self-explanatory, Pool is

pooling, which does nonlinear downsizing on the TPU; and TPU application popularity in July 2016. One DNN is RankBrain [Cla15]; one

LSTM is a subset of GNM Translate [Wu16]; one CNN is Inception; and the other CNN is DeepMind AlphaGo [Sil16][Jou15].

2. TPU Origin, Architecture, and Implementation

Starting as early as 2006, we discussed deploying GPUs, FPGAs, or custom ASICs in our datacenters. We concluded that the

few applications that could run on special hardware could be done virtually for free using the excess capacity of our large

datacenters, and it’s hard to improve on free. The conversation changed in 2013 when we projected that DNNs could become

so popular that they might double computation demands on our datacenters, which would be very expensive to satisfy with

conventional CPUs. Thus, we started a high-priority project to quickly produce a custom ASIC for inference (and bought

off-the-shelf GPUs for training). The goal was to improve cost-performance by 10X over GPUs. Given this mandate, the TPU

was designed, verified [Ste15], built, and deployed in datacenters in just 15 months. (Space limits the amount and the level of

detail on the TPU in this paper; see [Ros15a], [Ros15b], [Ros15c], [Ros15d], [Tho15], and [You15] for more.)

Rather than be tightly integrated with a CPU, to reduce the chances of delaying deployment, the TPU was designed to be

a coprocessor on the PCIe I/O bus, allowing it to plug into existing servers just as a GPU does. Moreover, to simplify

hardware design and debugging, the host server sends TPU instructions for it to execute rather than fetching them itself.

Hence, the TPU is closer in spirit to an FPU (floating-point unit) coprocessor than it is to a GPU.

Figure 1. TPU Block Diagram. The main computation part is the Figure 2. Floor Plan of TPU die. The shading follows Figure 1.

yellow Matrix Multiply unit in the upper right hand corner. Its inputs The light (blue) data buffers are 37% of the die, the light (yellow)

are the blue Weight FIFO and the blue Unified Buffer (UB) and its compute is 30%, the medium (green) I/O is 10%, and the dark

output is the blue Accumulators (Acc). The yellow Activation Unit (red) control is just 2%. Control is much larger (and much more

performs the nonlinear functions on the Acc, which go to the UB. difficult to design) in a CPU or GPU

The goal was to run whole inference models in the TPU to reduce interactions with the host CPU and to be flexible

enough to match the NN needs of 2015 and beyond, instead of just what was required for 2013 NNs. Figure 1 shows the block

diagram of the TPU.

The TPU instructions are sent from the host over the PCIe Gen3 x16 bus into an instruction buffer. The internal blocks

are typically connected together by 256-byte



-wide paths. Starting in the upper-right corner, the Matrix Multiply Unit



is the

heart of the TPU. It contains 256x256 MACs that can perform 8-bit multiply-and-adds on signed or unsigned integers. The

16-bit products are collected in the 4 MiB of 32-bit Accumulators



below the matrix unit. The 4MiB represents 4096,

256-element, 32-bit accumulators. The matrix unit produces one 256-element partial sum per clock cycle. We picked 4096 by

first noting that the operations per byte need to reach peak performance (roofline knee in Section 4) is ~1350, so we rounded

that up to 2048 and then duplicated it so that the compiler could use double buffering while running at peak performance.

When using a mix of 8-bit weights and 16-bit activations (or vice versa), the Matrix Unit computes at half-speed, and it

computes at a quarter-speed when both are 16 bits. It reads and writes 256 values per clock cycle and can perform either a

matrix multiply or a convolution. The matrix unit holds one 64KiB tile of weights plus one for double-buffering (to hide the

256 cycles it takes to shift a tile in). This unit is designed for dense matrices. Sparse architectural support was omitted for

time-to-deploy reasons. Sparsity will have high priority in future designs.

The weights for the matrix unit are staged through an on-chip Weight FIFO



that reads from an off-chip 8 GiB DRAM

called Weight Memory



(for inference, weights are read-only; 8 GiB supports many simultaneously active models). The weight

FIFO is four tiles deep. The intermediate results are held in the 24 MiB on-chip Unified Buffer



, which can serve as inputs to

the Matrix Unit. A programmable DMA controller transfers data to or from CPU Host memory and the Unified Buffer.

Figure 2 shows the floor plan of the TPU die. The 24 MiB Unified Buffer is almost a third of the die and the Matrix

Multiply Unit is a quarter, so the datapath is nearly two-thirds of the die. The 24 MiB size was picked in part to match the

pitch of the Matrix Unit on the die and, given the short development schedule, in part to simplify the compiler (see Section 7).

Control is just 2%. Figure 3 shows the TPU on its printed circuit card, which inserts into existing servers like an SATA disk.

As instructions are sent over the relatively slow PCIe bus, TPU instructions follow the CISC tradition, including a repeat

field. The average clock cycles per instruction (CPI) of these CISC instructions is typically 10 to 20. It has about a dozen

instructions overall, but these five are the key ones:

1. Read_Host_Memory reads data from the CPU host memory into the Unified Buffer (UB).

2. Read_Weights reads weights from Weight Memory into the Weight FIFO as input to the Matrix Unit.

3. MatrixMultiply/Convolve causes the Matrix Unit to perform a matrix multiply or a convolution from the

Unified Buffer into the Accumulators. A matrix operation takes a variable-sized B*256 input, multiplies it by a

256x256 constant weight input, and produces a B*256 output, taking B pipelined cycles to complete.

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skyePan

2017-11-09

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ncf25

2019-03-15

很好的论文
九章子

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不好，不是全部的详解，只有一点
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IEEE可直接下载
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