• ug998-vivado-intro-fpga-design-hls.pdf

    Introduction to FPGA Design with Vivado High-Level Synthesis UG998 (v1.1) January 22, 2019。 Software is the basis of all applications. Whether for entertainment, gaming, communications, or medicine, many of the products people use today began as a software model or prototype. Based on the performance and programmability constraints of the system, the software engineer is tasked with determining the best implementation platform to get a project to market. To accomplish this task, the software engineer is aided by both programming techniques and a variety of hardware processing platforms.

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  • ug902-vivado-high-level-synthesis.pdf

    Vivado Design Suite User Guide High-Level Synthesis。 UG902 (v2018.3) December 20, 2018。 The Xilinx® Vivado® High-Level Synthesis (HLS) tool transforms a C specification into a register transfer level (RTL) implementation that you can synthesize into a Xilinx field programmable gate array (FPGA). You can write C specifications in C, C++, or SystemC, and the FPGA provides a massively parallel architecture with benefits in performance, cost, and power over traditional processors. This chapter provides an overview of high-level synthesis.

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  • ug871-vivado-high-level-synthesis-tutorial.pdf

    High-Level Synthesis,UG871 (v2018.3) December 5, 2018。This Vivado® tutorial is a collection of smaller tutorials that explain and demonstrate all steps in the process of transforming C, C++ and SystemC code to an RTL implementation using High-Level Synthesis. The tutorial shows how you create an initial RTL implementation and then you transform it into both a low-area and high-throughput implementation by using optimization directives without changing the C code. The following sections describe a summary of each tutorial

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  • BCD转余3码串进串出分析.pdf

    BCD 转余 3 码串进串出分析,选自王建民书中例 8-17。余 3 码只要对 8421 编码加 3 即可得到。故,如果输入是并行的 8421 编码,输出是并行的余 3 码,则可以 直接通过一个加法器得到相应的余 3 码。但现在输入是串行的 8421 编码,输出是串行的余 3 码。一旦是串行的,就涉及到时序电路

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  • USB 3_0 Adopters Agreement Final_020411.pdf

    Notice: This agreement is not effective until a fully executed original has been received by the Secretary, Intel Corporation, at 2111 NE 25t Avenue, Mailstop JF5-373, Hillsboro, OR 97124. Attn: Brad Saunders. This agreement will not be effective if received by the Secretary after ex-piration of the Adoption Period (as defined in Section 1.3 below).

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  • JESD84-B51.pdf

    Embedded Multi-Media Card (e•MMC) Electrical Standard (5.1) JESD84-B51 (Revision of JESD84-B50.1, July 2014)

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  • SD-Host-Controller-Simplified-SpecificationV4.20.pdf

    SD Specifications Part A2 SD Host Controller Simplified Specification Version 4.20 April 10, 2017

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  • phy-interface-pci-express-sata-usb30-architectures-3-1.pdf

    PIPE协议,PHY Interface For the PCI Express, SATA, USB 3.1, DisplayPort, and Converged I0 Architectures Version 5.2.1

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  • extensible-host-controler-interface-usb-xhci-1.1(解密有书签).pdf

    xHCI1.1协议,解密板,有书签。eXtensible Host Controller Interface for Universal Serial Bus (xHCI) Requirements Specification November 2017 Revision 1.1

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  • SystemVerilog_IEEE 1800.2-2017.pdf

    SystemVerilog 的Ieee1800标准,2017板,主要内容是关于UVM,即IEEE Standard for Universal Verification Methodology Language Reference Manual

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