计算机组成原理实验一

module Fadd(x,y,Cin,Cout,Sum); input x,y,Cin; output Cout,Sum; wire a,b,c; xor (a,x,y); xor (Sum,a,Cin); and (b,x,y); and (c,Cin,a); or (Cout,b,c); endmodule 测试程序： module test; // Inputs reg x; reg y; reg Cin; // Outputs wire Cout; wire Sum; // Instantiate the Unit Under Test (UUT) add uut ( .x(x), .y(y),