CMOS模拟集成电路版图设计软件教程.pdf(pdf格式ppt)
CMOS模拟集成电路版图设计软件教程
0.18um Floating Gate EEPROM Simple PROCESS FLOW Fully Embedded with SMIC 0.18um Logic Process 1.8v Logic Core + 3.3v/5v MV (Option) + 16v HV + EEPROM Integrate ROM + OTP + EEPROM on one chip Retrograde Twin Well + HVNW + Psub , 2P3M ~ 5M 31 Masks, 31 Masking Steps (2P5M), 10 extra litho for EEPROM Foundry-Competitive EEPROM Bit Cell Size > 100K Write/Erase cycles >40Yr Data Retention
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