intel-xeon-scalable-processor-throughput-latency.pdf

The table describes throughput and latency for processors with two FMA units, assuming all sources come from the FMA unit. See FMA latency chapter in the optimization guide for more information. Memory latencies are assuming Data Cache Unit (DCU) hit

64-ia-32-architectures-optimization-manual.pdf

The Intel® 64 and IA-32 Architectures Optimization Reference Manual describes how to optimize software to take advantage of the performance characteristics of IA-32 and Intel 64 architecture processors. The target audience for this manual includes software programmers and compiler writers. This manual assumes that the reader is familiar with the basics of the IA-32 architecture and has access to the Intel® 64 and IA-32 Architectures Software Developer’s Manual. A detailed understanding of Intel 64 and IA-32 processors is often required. In many cases, knowledge of the underlying microarchitectures is required. The design guidelines that are discussed in this manual for developing high-performance software generally apply to current as well as to future IA-32 and Intel 64 processors. In most cases, coding rules apply to software running in 64-bit mode of Intel 64 architecture, compatibility mode of Intel 64 architecture, and IA-32 modes (IA-32 modes are supported in IA-32 and Intel 64 architectures). Coding rules specific to 64-bit modes are noted separately

Intel® 64 and IA-32 Architectures Software Developer’s Manual Combined.pdf

Volume 1: Describes the architecture and programming environment of processors supporting IA-32 and Intel® 64 architectures. Volume 2: Includes the full instruction set reference, A-Z. Describes the format of the instruction and provides reference pages for instructions. Volume 3: Includes the full system programming guide, parts 1, 2, 3, and 4. Describes the operating-system support environment of Intel® 64 and IA-32 architectures, including: memory management, protection, task management, interrupt and exception handling, multi-processor support, thermal and power management features, debugging, performance monitoring, system management mode, virtual machine extensions (VMX) instructions, Intel® Virtualization Technology (Intel® VT), and Intel® Software Guard Extensions (Intel® SGX). Volume 4: Describes the model-specific registers of processors supporting IA-32 and Intel® 64 architectures.

CN71XX-HM-0.991E.pdf

The Cavium OCTEON III CN71XX Multicore cnMIPS64 processors are a family of processors targeted at intelligent networking, wireless, control-plane, and storage applications. The CN71XX is targeted for many applications, but is particularly wellsuited for the following applications and standards:

P4080 Errata Sheet.pdf

This document details all known silicon errata for the P4080 and P4040. The following table provides a revision history for this document.

P4080_Reference_Manual,_Rev_G.pdf

This reference manual defines the functionality of the P4080 QorIQ Integrated Host Controller. This device integrates eight PowerPC™ processor cores based on Power Architecture™ technology, two frame manager units, other datapath acceleration blocks, with system logic required for networking, telecommunications, and wireless infrastructure applications. The e500mc processor core is a low-power implementation of the family of reduced instruction set computing (RISC) embedded processors that implement the Book E definition of the Power Architecture

E6500RM.PDF

e6500 Core Reference Manual This core reference manual includes the register model, instruction model, MMU, memory subsystem, and debug and performance monitor facilities of the e6500 core. The primary objective of this manual is to describe the functionality of the e6500 embedded microprocessor core for software and hardware developers

Memory Management Examples.pdf

This set of examples shows how to set up the Memory Management Unit (MMU) in a bare metal environment. The examples walk through sets of code, building on the overall explanation of the MMU and translation process that the Memory management guide provides.

Exception model.pdf

This guide introduces the exception and privilege model in Armv8-A. This guide covers the different types of exceptions in the Arm architecture, and the behavior of the processor when it receives an exception

Armv8-A memory model guide.pdf

This guide introduces the memory model in Armv8-A. It begins by explaining where attributes that describe memory come from and how they are assigned to regions of memory. Then it introduces the different attributes that are available and explains the basics of memory ordering