EP2C8开发板原理图
Altera EP2C8 FPGA开发板原理图
Cyclone II Device Handbook (All Sections) Section I. Cyclone II Device Family Data Sheet •Chapter 1. Introduction (ver 3.2, Feb 2008, 168 KB) •Chapter 2. Cyclone II Architecture (ver 3.1, Feb 2007, 628 KB) •Chapter 3. Configuration & Testing (ver 2.2, Feb 2007, 141 KB) •Chapter 4. Hot Socketing & Power-On Reset (ver 3.1, Feb 2007, 125 KB) •Chapter 5. DC Characteristics and Timing Specifications (ver 4.0, Feb 2008, 1 MB) •Chapter 6. Reference & Ordering Information (ver 1.4, Feb 2007, 85 KB) Section II. Clock Management •Chapter 7. PLLs in Cyclone II Devices (ver 3.1, Feb 2007, 417 KB) Section III. Memory •Chapter 8. Cyclone II Memory Blocks (ver 2.4, Feb 2008, 379 KB) •Chapter 9. External Memory Interfaces (ver 3.1, Feb 2007, 333 KB) Section IV. I/O Standards •Chapter 10. Selectable I/O Standards in Cyclone II Devices (ver 2.4, Feb 2008, 461 KB) •Chapter 11. High-Speed Differential Interfaces in Cyclone II Devices (ver 2.2, Feb 2007, 281 KB) ◦Readme File for x8 Mode & LVDS SERDES ◦Reference Design for x8 Mode & LVDS SERDES Section V. Digital Signal Processing (DSP) •Chapter 12. Embedded Multipliers in Cyclone II Devices (ver 1.2, Feb 2007, 152 KB) Section VI. Configuration & Testing •Chapter 13. Configuring Cyclone II Devices (ver 3.1, Feb 2007, 678 KB) •Chapter 14. IEEE 1149.1 (JTAG) Boundary Scan Testing for Cyclone II Devices (ver 2.1, Feb 2007, 258 KB) Section VII. PCB Layout Guidelines •Chapter 15. Package Information for Cyclone II Devices (ver 2.3, Feb 2007, 1 MB)