FPGA-CPLD芯片

hijian a1(time1,time2,time3,time4,time5,time6,clk_16); shaomiao b1(clk,c1[3],c1[2],c1[1],c1[0],c2[3],c2[2],c2[1],c2[0],time1,time2,time3,time4,time5,time6,shi1,shi2); decode4_7 d1(p1[6],p1[5],p1[4],p1[3],p1[2],p1[1],p1[0],shi1[3],shi1[2],shi1[1],shi1[0]); decode4_7 d2(p2[6],p2[5],p2[4],p2[3],p2[2],p2[1],p2[0],shi2[3],shi2[2],shi2[1],shi2[0]); endmodule

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