Bringing Agile Methods Into Functional Verification

Agile Programming is a highly disciplined methodology used in software engineering. One aspect of the Agile methodology that is applicable to ASIC/FPGA functional verification and particularly important when creating verification environments using an Object Oriented paradigm is the Test Driven Development [2]. This process encourages the creation of a separate unit test for every critical class that is defined in a system. This paper describes the value of using a SystemVerilog unit test framework when creating a functional verification environment. Applying this Agile aspect may help achieve improvements in both quality and productivity. The usage model, the design of a unit test framework created for SystemVerilog (called svunit), and a concrete example of its usage are also presented.

Implementing Layered Stimulus Models Using Implicit Encapsulation

This paper proposes a method called implicit encapsulation for creating layered stimulus models for use in constrained random verification environments. The proposed method relies heavily on the VMM class library – the atomic generator and scenario generator in particular – along with techniques typical of transaction level modeling. A set of generic components and a scalable structure is described that enables the creation of layered protocol stacks in a variety of arrangements. The intended audience includes those verifying medium to large RTL blocks that process layered protocols.

Attacking Constraint Complexity in Verification IP Reuse

As chip design becomes larger and more complex, verification engineers are expanding constrained-random testing to meet the validation demand. The size and complexity of constraint problems are growing, resulting in performance and capacity issues. This paper discusses the key challenges verification engineers face when writing constraints – how to achieve test goals, how to optimize constraints for performance and how to manage the interaction and code complexity. We use two case studies from the network domain to illustrate these issues.

Multi-Stream ScenariosEnhancing Stimulus Generation in the VMM_paper.pdf

Today's verification solutions often require complex concurrent streams of stimulus controlled from higher level transactors or scenarios. The VMM 1.1 library has been enhanced to add this capability, and support the management of access to the resources shared by different stimulus streams, i.e. multiple streams providing stimulus to the same transactor. This paper describes the challenges faced in developing these new features, and takes a detailed look at how they are used in a VMM “multi-stream scenario” environment.

Performance Verification of a Complex Bus Arbiter

This paper describes the use of the VMM Performance Analyzer to verify the performance of an AXI-based bus arbiter. The goal of performance verification is to verify that the architectural intent of the arbiter is fulfilled. The arbiter must provide specified bandwidth and latency to each bus master. To measure arbiter performance, we used a new VMM Application – the VMM Performance Analyzer. This application allows the collection of arbitrary user-defined performance data into an SQL database. We show how this application was integrated into our existing VMM testbench and how we post-processed the SQL data to quantify the arbiter’s performance.

An XML-Based Flow for RAL

This paper covers the lessons learned while integrating RAL in an automated register definition flow from Word document specification to Testbench infrastructure genera-tion and RTL implementation. It includes the initial thought process involved in archi-tecting the environment, the choice of a XML repository to close the gap between the RAL format and the Word doc format, the use of a layered approach with constrainable functional configuration defined separately at the transaction generation level and with the RAL classes coupled with a mapping layer at the driver level, and the definition of separate layers of functional coverage instrumentation beyond the native set.

Is SystemVerilog Useful for FPGA Design

SystemVerilog has gained rapid acceptance as a powerful ASIC and custom IC design and verification language. Are FPGA designers also using SystemVerilog? Which SystemVerilog features have they found useful? This paper answers these questions based on the experiences from several companies that have recently tried using SystemVerilog for designing and verifying FPGA designs. The paper summarizes what has worked well—and what has not work well—at each of these companies.

project.management.survival

Part I. Understanding Projects 1. What Are Projects and Why Do They Fail? 5 What is a project? 5; What is project management? 6; Why is it vital to manage projects well? 8; Project killers 9 2. Dead Project Walking – Why some projects must be killed 13 Why dead projects live on 14 Part II. Where are We? 3. Diagnosing an Existing Project 19 Why doing a diagnostic makes sense 19; Getting to the truth 20; Digging into the plan 24; Diagnosing a multicompany programme 28 Part III. Getting the Right Initial Plan 4. Leading Projects 33 The wrong kind of project managers 33; Being the right kind of project manager 34; Give the team responsibility 35; Managing in a matrix 36; Being a team player 37; Overcoming ‘It can’t be done’ 38; Focusing your attention in the right places 41 5. Project Scope and Initiation 44 Introduction 44; Project initiation 45; The Project Charter 48; Creating the Project Charter 48; Get it right early on – it’s cheaper 50; Summary and actions 56 6. Agreeing Objectives 57 Why objectives are important 57; Developing welldefined objectives 59; Good and bad objectives – some examples 61; Summary and actions 65 7. Milestones 66 The problem with bad milestones 67; How to write a good milestone 68; Writing milestones 70; Differences between milestones and gates 70; Summary and actions 74 8. Refining Milestones 76 Do you have the right milestones? 76; How result paths help 76; Setting up result paths 77; Assessing result paths 79; Developing the detail for each milestone 82; Beyond milestones 82; Summary and actions 83 9. Activities/Work Breakdown Structure 85 What is a work breakdown structure? 86; The work breakdown structure underpins much of the planning 89; The rolling wave approach 90; The impact of rolling wave on estimation and contingency 91; Summary and actions 93 10. Assigning Resources 96 Identifying the resources you need 96; Summary and actions 98 11. Time Estimation 100 Why estimation goes wrong 100; Why managing using ‘percentage complete’ doesn’t work 102; A better approach for estimation – work content 106; Producing good estimates 108; Record any assumptions used in estimation 111; Summary and actions 112 12. Resource Availability 114 Estimating task durations from the work content 114; Summary and actions 122 13. Dependencies 124 Different types of dependencies 125; Lag 126; Predecessors and successors 128; Tasks and subtasks 129; Critical path 131; Slack/float 133; Summary and actions 134 14. Risk and Mitigation 136 The problems with simple risk/contingency planning 137; Identifying and managing risks 137; Risk identification 138; Risk assessment 139; Risk reduction 143; Risk management 145; Summary and actions 146 Part IV. Getting the Plan Right 15. Optimizing the Plan 151 Create more realistic resource usage 152; Improve resource usage to shorten the duration of key tasks 153; Reducing task durations on the critical path 157; Working in parallel 157; Optimization and risk 158; Project crashing 160; Developing the project budget 163; Where you end up is where you start 163 Part V. Staying on Track 16. Roles, Responsibilities and Communication 167 Project manager 167; Work package or module managers 169; Project team members 169; Project sponsor 170; Project office 171; Steering group 171; Communication between the roles 172; Project manager’s weekly checklist 175 17. Updating the Plan 178 The update information you need from team members 178; Integrating the updates 179; Updating the plan in practice 181; How often? 182 18. Monitoring Progress 183 Introduction 183; How to monitor progress within a project 184; Earned Value Analysis (EVA) 186; Using EVA to monitor progress 190; Limitations of EVA 193 19. Handling Issues 194 Introduction 194; What is an issue? 195; Prioritizing issues 195; Managing issues 195 20. Controlling Change 197 21. Reporting 201 Reporting down 201; Reporting up 202 22. Project Closure 203 Appendix 1: The Changing Nature of Projects 205 Appendix 2: Project Management Software 211 Appendix 3: Project Management Approaches and Methodologies 219 Appendix 4: Problem-solving Techniques 229 Appendix 5: References and Resources 233 Index 235

sed & awk (2nd)

Chapter 1: Power Tools for Editing Chapter 2: Understanding Basic Operations Chapter 3: Understanding Regular Expression Syntax Chapter 4: Writing sed Scripts Chapter 5: Basic sed Commands Chapter 6: Advanced sed Commands Chapter 7: Writing Scripts for awk Chapter 8: Conditionals, Loops, and Arrays Chapter 9: Functions Chapter 10: The Bottom Drawer Chapter 11: A Flock of awks Chapter 12: Full-Featured Applications Chapter 13: A Miscellany of Scripts Appendix A: Quick Reference for sed Appendix B: Quick Reference for awk Appendix C: Supplement for Chapter 12

If Chained Implications in Properties Weren't So Hard, They'd Be Easy

If Chained Implications in Properties Weren't So Hard, They'd Be Easy_pres.pdf