AN-120 Capacitive Coupling for Ethernet Transceiver-decrypted
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Application Note 120
Capacitive Coupling Ethernet Transceivers
without Using Transformers
Micrel 10/100 Ethernet Products
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
January 2006
M9999-011606
General Description
It is a common practice to capacitively couple Ethernet
transceivers (PHYs) together without the use of a transformer to
reduce both the BOM cost and PCB area. This application note
describes methods for capacitive coupling of Micrel’s 10/100
Ethernet devices.
Micrel Devices for Capacitive Coupling
KS8695X CENTAUR – Integrated Multi-port Gateway
Solution
KS8695P/PX CENTAUR – Integrated Multi-port PCI
Gateway Solution
KS8721B/BT Single Port 10/100 PHY with Auto MDI/MDI-X
Crossover
KS8721BL/SL 3.3V Single Power Supply 10/100 PHY with
Auto MDI/MDI-X Crossover
KS8993 3-Port 10/100 Unmanaged Switch
KS8993F 3-Port 10/100 Managed/Unmanaged
Switch/Media Converter with TS-1000 OAM
KS8993M 3-Port 10/100 Managed/Unmanaged Switch
KS8995M/X 5-Port 10/100 Managed/Unmanaged Switch
KS8995MA/XA 5-Port 10/100 Managed/Unmanaged Switch
KS8997 8-Port 10/100 Unmanaged Switch
KS8999 9-Port 10/100 Unmanaged Switch
Methods for Capacitive Coupling
The method for capacitive coupling depends upon whether or not
the receiver circuit provides an internal DC bias offset.
Transmit Termination
Figures 1 and 2 show the capacitive coupling for transmit-side
termination. In this method, the 50Ω pull-up resistors R1 and R2
are pulled up to analog V
DD
. All Micrel devices listed in this
application note require this output termination, except for the
KS8993 device.
For the KS8993, R1 and R2 are tied together, but not to V
DD
. The
TXPx and TXMx differential signals are each terminated with
50Ω pull-ups to the port’s VREFx pin.
Receive Termination for Devices with Internal DC Bias
Figure 1 shows the circuit diagram for capacitive coupling to a
receiver with internal DC biasing. The 50Ω pull-up resistors R3
and R4 are capacitively coupled via C3 to analog V
DD
, providing
the correct receiver input termination. This method is applicable
to the KS8993, which provides internal DC biasing.
V
DD
V
DD
Figure 1. Capacitive Coupling Circuit Diagram for Receivers
with Internal DC Bias
Receive Termination for Devices without Internal DC
Bias
Figure 2 shows the circuit diagram for capacitive coupling to a
receiver without internal DC biasing. In this illustration, the
50Ω pull-up resistors R3 and R4 on the receiver inputs provide
the necessary DC offset. These 50Ω resistors also provide the
input termination.
This method is applicable to the KS8695X, KS8695P/PX,
KS8721B/BT, KS8721BL/SL, KS8993M/F, KS8995M/X, and
KS8995MA/XA, none of which provide internal DC biasing.
V
DD
V
DD
Figure 2. Capacitive Coupling Circuit Diagram for Receivers
without Internal DC Bias
Transmit /Receive Termination for KS8997 and KS8999
Figure 2 shows the capacitively coupling between two KS8997 or
KS8999 devices. It is necessary to choose pull up resistor values
(R1, R2, R3, and R4) that will provide the DC offset for the
transmit differential pair Txdc level greater than 1.3V in order to
maintain a reasonable and balanced swing. To accomplish this,
the following values should be utilized:
VDD = 2.1V (typ)
R1, R2, R3, R4 = 33 ohms
Txdc = 1.44V (VDD-20mA x 33ohms)
Swing = +/- 330mV (20mA x 33/2 ohms)
or
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