AR8327手册资源-CSDN文库

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### AR8327七端口千兆以太网交换机技术手册 #### 一、产品概述 **AR8327**是一款高度集成的七端口千兆以太网交换机芯片，由Atheros Communications, Inc.设计制造。该芯片具备非阻塞式交换结构、高性能查找单元（支持2048个MAC地址）、以及四类流量级别的服务质量(QoS)引擎。这些特性使得AR8327能够在多种网络环境中灵活应用。 #### 二、关键特性与功能 ##### 1. 高度集成 AR8327集成了高速交换系统的所有主要功能，包括包缓存、物理层收发器(PHY Transceivers)、媒体访问控制器(MAC)、地址管理以及非阻塞式交换结构等，所有这些都在一个0.11微米的CMOS芯片上实现。 ##### 2. 网络兼容性 - **符合标准**：该芯片完全符合10BASE-Te、100BASE-Tx和1000BASE-T的标准规范，包括MAC控制、暂停帧及自动协商子层等部分。 - **兼容性广泛**：支持与所有行业标准的以太网、快速以太网及千兆以太网网络兼容。 ##### 3. 高性能查找单元 AR8327内置了高性能的查找单元，能够存储多达2048个MAC地址，从而确保数据包的高效转发。 ##### 4. 四级QoS引擎该芯片支持四级流量级别的服务质量引擎，可以对不同类型的网络流量进行优先级排序，确保关键应用和服务的质量不受影响。 ##### 5. 灵活性 - **多端口配置**：包含五个全双工10BASE-Te/100BASE-TX/1000BASE-T收发器，每个收发器都能够执行10BASE-Te以太网上所有物理层接口的功能，适用于五类非屏蔽双绞线(UTP)电缆。 - **扩展能力**：剩余两个端口提供标准GMII/RGMII/MII/Serdes接口，以便连接到主机或其他网络设备。 #### 三、应用场景 - **无线接入点路由器**：适用于需要高性能网络交换的无线接入点和路由器。 - **家庭网关**：满足现代家庭网络对于高速数据传输的需求。 - **xDSL/电缆调制解调器平台**：适用于各种宽带接入方案，如ADSL、VDSL或有线调制解调器。 #### 四、技术规格 - **端口数量**：七个千兆以太网端口。 - **非阻塞式架构**：确保数据包在交换过程中不会发生拥塞。 - **MAC地址容量**：支持高达2048个MAC地址的存储。 - **QoS机制**：四级流量级别的服务质量控制。 - **接口类型**： - 五个10BASE-Te/100BASE-TX/1000BASE-T端口。 - 两个可选GMII/RGMII/MII/Serdes接口。 - **物理层支持**：支持五类非屏蔽双绞线(UTP)电缆。 #### 五、优势分析 - **成本效益**：通过高度集成的设计减少了外部组件的需求，降低了整体成本。 - **高性能**：非阻塞式架构和高性能查找单元确保了数据传输的速度和效率。 - **灵活性**：支持多种网络应用和配置选项，适应不同的部署环境。 AR8327是一款针对成本敏感型网络应用而设计的高性能七端口千兆以太网交换机芯片，适用于无线接入点路由器、家庭网关和xDSL/电缆调制解调器平台等多种场景。其强大的功能和灵活性使其成为现代网络基础设施的理想选择。

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COMPANY CONFIDENTIAL • 1

Data Sheet

Orion®, PLC4Trucks®, Powerpacket®, Spread Spectrum Carrier®, SSC®, ROCm®, Super A/G®, Super G®, Super N®, The Air is Cleaner at 5-GHz®, Total 802.11®, U-

Nav®, Wake on Wireless®, Wireless Future. Unleashed Now.®, and XSPAN®, are registered by Atheros Communications, Inc. Atheros SST™, Signal-Sustain Technology™,

Ethos™, Install N Go™, IQUE™, ROCm™, amp™, Simpli-Fi™, There is Here™, U-Map™, U-Tag™, and 5-UP™ are trademarks of Atheros Communications, Inc. The

Atheros logo is a registered trademark of Atheros Communications, Inc. All other trademarks are the property of their respective holders. Subject to change without notice.

June 2011

Version 1.0

AR8327/AR8327N Seven-port Gigabit Ethernet Switch

General Description

The AR8327 is a highly integrated seven-port

Gigabit Ethernet switch with non-blocking

switch fabric, a high-performance lookup unit

with 2048 MAC address, and a four-traffic class

Quality of Service (QoS) engine. The AR8327

has the flexibility to support various networking

applications. The AR8327 is designed for cost-

sensitive switch applications in wireless AP

routers, home gateways, and xDSL/cable

modem platforms.

The AR8327

integrates all the functions of a

high-speed Switch system, including packet

buffer, PHY transceivers, media access

controllers, address management, and a non-

blocking switch fabric into a single 0.11 um

CMOS device. It complies with 10BASE-Te,

100BASE-Tx & 1000BASE-T specifications,

including the MAC control, pause frame, and

auto-negotiation subsections, providing

compatibility with all industry-standard

Ethernet, Fast Ethernet & Gigabit Ethernet

networks.

The AR8327 device contains five full-duplex

10BASE-Te/100BASE-TX/1000BASE-T

transceivers and 10BASE-Te/100BASE-TX can

run at half duplex, each of which performs all

of the physical layer interface functions for

10BASE-Te Ethernet on Category 5 unshielded

twisted-pair (UTP) cable and 100BASE-TX

Fast/Gigabit Ethernet on Category 5 UTP

cable. The remaining 2 ports feature a standard

GMII/RGMII/MII/Serdes interface to allow

connection to a host CPU in PON/xDSL/

Cable/Wifi/Fiber routers. The media access

controllers on the AR8327 also support Jumbo

Frames which are typically used for high-

performance connections to servers because

they offer a smaller percentage of overhead on

the link for more efficiency.

MDC/MDIO or EEPROM interfaces provide

easy programming of the on-chip 802.1p QoS

and/or DiffServ/TOS. This allows switch

traffic to be given different classes of priority or

service - for example, voice traffic for IP phone

applications, video traffic for multimedia

applications, or data traffic for e-mail. Up to 4K

Virtual LANs (VLANs) can be set up via the

MDC/MDIO port for separation of different

users or groups on the network. ACL features

can reduce CPU effort for VLAN/Q.O.S/

DSCP/Forward mapping & remapping based

on layer1 to Layer4 information. 16 PPPoE

header add/removal can increase Video

quality and offload the CPU. Hardware IGMP

V1/V2/V3 is an innovation for IPTV service.

Green Power can increase energy efficiency for

no link or idle states.

The AR8327N chip supports hardware NAT

(Network Address Translation) to offload the

CPU and achieve the full wire speed when

doing NAT. The AR8327/AR8327N supports

the following modes of NAT.

1. Basic NAT: This involves IP address

translation only, not port mapping.

2. Network Address Port Translation (NAPT):

This involves the translation of both IP

addresses and port numbers. For the NAPT

mode, the AR8327/AR8327N can support

Full cone NAT, Restricted cone NAT, Port-

Restricted cone NAT and Symmetric NAT.

e AR8327/AR8327N supports the following

configurations

n 5*10/100/1000Base-T + GMII/RGMII/MII

+ 1* Serdes

n 5* 10/100/1000Base-T + 2*RGMII/MII

n 4* 10/100/1000Base-T + 1*RGMII/MII + 1*

Single RGMII PHY

AR8327/AR8327N Features

The AR8327 chip family includes a 7-port MAC

structure to support the following family of

switch chips:

n Supports 802.3az Power Management

n The AR8327N chip includes the Hardware

NAT (Network Address Translation)

function

2 • AR8327/AR8327N Seven-port Gigabit Ethernet Switch Atheros Communications, Inc.

2 • June 2011 COMPANY CONFIDENTIAL

n The AR8327 chip (without the ‘N’

designation) does not contain the Hardware

NAT function

n ACL Mask Rule from Layer1~4. Port No,

DA, SA, Ethernet Type, VLAN, IP Protocol,

IPv4/v6 Source/Destination Address,

TCP/UDP Source/Destination port

n 96 ACL Mask Rule for Pass/Drop, VLAN/

Q.O.S./DSCP Mapping/Translation

n User define ACL up to 48 bytes depth in

Layer 4/3/2

n Q.O.S mechanisms include Weight Round

Robin, Strict, Hybrid Up Queue

n Port Base VLAN & 4K 802.1Q VLAN Group

n IVL & SVL

n IGMP Snooping V1, V2 & V3. IPv6 MLD V1/

V2 forwarded to CPU

n Supports Light Hardware IGMP snooping

v1/v2/v3, MLDv1/v2 and Smart Leave

n Hardware Looping Detection

n QinQ function for SVLAN & CVLAN

Translation

n IP Packet/PPPoE bypass to reduce CPU

loading on Video packet

n 16 PPPoE session support/PPP Session

Header Removal/Addition

n Scalable Ingress/Egress Bandwidth Control

n 40 MIBs Counter/Port & Port Status.

n 1M Bit Packet Buffer

n Supports 9K Jumbo Frame

n Port Mirror, 802.1X Security, Rapid Spanning

Tree

n Rule-based Bandwidth Control

n Programmable Wake on LAN

n Half Power Mode for Cable length less than

30m (for home installations)

n Supports Internal/External Loopback

n Supports Reduced AFE circuit

n 2K MAC Table. Edit, Search, Add & Delete.

n MAC Limit by Port/Chip/VLAN

n Trunking Function

n Supports Trunking and auto-failover

n Power Saving on Cable no Link, short Cable

& 10BASE-Te Idle

n Supports 1K NAPT entries and 128

hardware based host routing (ARP) entries

n Supports hardware-based IP source guard,

ARP inspection, routing/L3 switching

n Supports VLAN translation and mapping

with 64 Translation entries

n 148 pin DRQFN, 0.11um

AR8327 System Block Diagram

Configuration

Registers

MB/Statistics

Counters

LED

Controller

MDC/MDIO

QoS Engine

Buffer Memory

VLAN Table

Lookup Engine

MAC Table Memory

Queue Manager

Bandwidth Control

7-Port Gigabit Ethernet Switch Engine

Port 0

GMAC

GMII /

RGMII

Port 1

GMAC

10 /100 /1000

Based -T

PHY

Port 2

GMAC

Port 3

GMAC

Port 4

GMAC

Port 5

GMAC

EEPROM

LED

MDC/

MDIO

10/100 /1000

Based -T

PHY

10 /100 /1000

Based -T

PHY

10 /100 /1000

Based -T

PHY

10 /100 /1000

Based -T

PHY

RGMII

Port 6

GMAC

Serdes

Port 0

Atheros Communications, Inc. AR8327/AR8327N Seven-port Gigabit Ethernet Switch • 3

COMPANY CONFIDENTIAL June 2011 • 3

Table of Contents

General Description ........................................ 1

AR8327/AR8327N Features .......................... 1

AR8327 System Block Diagram .................... 2

Table of Contents ............................................ 3

Revision History ........................................... 11

1 Pin Descriptions .......................... 13

2 Functional Description ............... 23

2.1 Applications ............................................ 23

2.1.1 AP Router Application .............. 23

2.2 Atheros Header ...................................... 24

2.2.1 Transmit ....................................... 25

2.3 Receive ..................................................... 25

2.4 Header for Read/Write Register. ........ 26

2.5 Media Access Controllers (MAC) ........ 26

2.6 Port Status Configuration ..................... 26

2.6.1 Full-Duplex Flow Control ......... 26

2.6.2 Half-Duplex Flow Control ........ 26

2.6.3 Inter-Packet Gap (IPG) ............... 27

2.6.4 Illegal Frames .............................. 27

2.7 ACL .......................................................... 27

2.7.1 ACL Rule ..................................... 27

2.7.2 Action Definition ........................ 28

2.7.3 MAC Pattern ............................... 29

2.7.4 IPv4 Pattern ................................. 30

2.7.5 IPv6 Pattern ................................. 32

2.7.6 Window Pattern .......................... 34

2.7.7 Enhanced MAC Pattern ............. 35

2.7.8 Enhanced MAC Pattern ............. 35

2.8 Register Access ....................................... 36

2.9 LED Control ............................................ 37

2.10 VLANs .................................................... 38

2.10.1 Port-Based VLAN ....................... 38

2.10.2 802.1Q VLANs ............................ 38

2.10.3 VLAN Security ............................ 38

2.10.4 Port Isolation ............................... 39

2.10.5 Leaky VLAN ............................... 39

2.10.6 VLAN Translation ...................... 39

2.10.7 VLAN Translation Table ........... 39

2.10.8 Egress Mode ................................ 40

2.10.9 VLAN Table ................................. 41

2.11 Security and Port Mapping ................. 41

2.12 MIB/Statistics Counters ...................... 43

2.13 Quality of Service (QoS) ...................... 45

2.14 Mirroring ................................................ 45

2.15 Rate Limiting ......................................... 46

2.16 Broadcast Suppression ......................... 46

2.17 IGMP/MLD Snooping ......................... 46

2.17.1 IEEE 802.3 Reserved Group

Addresses Filtering Control ...... 46

2.17.2 802.1X ........................................... 46

2.17.3 Forwarding Unknown ............... 47

2.17.4 MAC Limit .................................. 47

2.18 Spanning Tree ....................................... 47

2.18.1 EEPROM Programming Format 47

2.18.2 Basic Switch Operation .............. 47

2.18.3 Lookup Engine ............................ 47

2.18.4 Automatic Address Learning ... 48

2.18.5 Automatic Address Aging ........ 48

2.18.6 Broadcast/Multicast Storm Control

2.18.7 ARL Table .................................... 48

2.19 HNAT ..................................................... 50

2.19.1 Basic NAT Table ......................... 50

2.19.2 NAPT Entry ................................. 51

2.19.3 Router MAC Address ................ 52

2.19.4 ARP ENTRY ................................ 53

2.20 IEEE 802.3az and Energy Efficient

Ethernet 53

2.20.1 IEEE 802.3az LPI Mode .............. 54

2.21 Memory Map ......................................... 55

3 Register Descriptions ..................57

3.1 Register Address Space (Address Range

0x0000 ~ 0x00FC) 57

3.2 Global Register Summary (Address Range

0x0000 ~ 0x00B4) 58

3.2.1 MASK_CTRL ............................... 59

3.2.2 PORT0 PAD MODE CTRL ........ 59

3.2.3 PORT5 PAD MODE CTRL ........ 60

3.2.4 PORT6 PAD MODE CTRL ........ 61

3.2.5 PWS_REG .................................... 63

3.2.6 GLOBAL_INT0 ........................... 64

3.2.7 GLOBAL_INT1 ........................... 65

4 • AR8327/AR8327N Seven-port Gigabit Ethernet Switch Atheros Communications, Inc.

4 • June 2011 COMPANY CONFIDENTIAL

3.2.8 GLOBAL_INT0 ........................... 66

3.2.9 GLOBAL_INT1 ........................... 67

3.2.10 MODULE_EN ............................. 68

3.2.11 MIB ................................................ 68

3.2.12 INTERFACE_HIGH_ADDR ..... 69

3.2.13 MDIO Master Control ................ 70

3.2.14 BIST_CTRL ..................................70

3.2.15 BIST_RECOVER .......................... 71

3.2.16 SERVICE_TAG ............................ 72

3.2.17 LED_CTRL0 ................................. 72

3.2.18 LED_CTRL1 ................................. 72

3.2.19 LED_CTRL2 ................................. 73

3.2.20 LED_CTRL3 ................................. 73

3.2.21 GOL_MAC_ADDR0 ................... 74

3.2.22 GOL_MAC_ADDR1 ................... 74

3.2.23 MAX_FRAME_SIZE ................... 74

3.2.24 PORT0_STATUS ......................... 75

3.2.25 PORT1_STATUS ......................... 76

3.2.26 PORT2_STATUS ......................... 77

3.2.27 PORT3_STATUS ......................... 78

3.2.28 PORT4_STATUS ......................... 79

3.2.29 PORT5_STATUS ......................... 80

3.2.30 PORT6_STATUS ......................... 81

3.2.31 HEADER_CTRL ..........................82

3.2.32 PORT0_HEADER_CTRL ........... 82

3.2.33 PORT1_HEADER_CTRL ........... 83

3.2.34 PORT2_HEADER_CTRL ........... 83

3.2.35 PORT3_HEADER_CTRL ........... 84

3.2.36 PORT4_HEADER_CTRL ........... 85

3.2.37 PORT5_HEADER_CTRL ........... 85

3.2.38 PORT6_HEADER_CTRL ........... 86

3.2.39 SGMII Control Register ............. 86

3.3 EEE CTRL REGISTER SUMMARY

(Address Range 0x0100 ~ 0x0168) 89

3.3.1 EEE_CTRL ................................... 89

3.3.2 EEE_LOC_VALUE_1 ................. 90

3.3.3 EEE_REM_VALUE_1 ................. 90

3.3.4 EEE_RES_VALUE_1 ................... 90

3.3.5 EEE_LOC_VALUE_2 ................. 90

3.3.6 EEE_REM_VALUE_2 ................. 91

3.3.7 EEE_RES_VALUE_2 ................... 91

3.3.8 EEE_LOC_VALUE_3 ................. 91

3.3.9 EEE_REM_VALUE_3 ................. 92

3.3.10 EEE_RES_VALUE_3 ...................92

3.3.11 EEE_LOC_VALUE_4 ................. 92

3.3.12 EEE_REM_VALUE_4 ................. 93

3.3.13 EEE_RES_VALUE_4 .................. 93

3.3.14 EEE_LOC_VALUE_5 ................. 93

3.3.15 EEE_REM_VALUE_5 ................. 94

3.3.16 EEE_RES_VALUE_5 .................. 94

3.4 PARSER REGISTER SUMMARY(Address

Range 0x0200 ~ 0x0270) 95

3.4.1 NORMALIZE_CTRL0 ................ 95

3.4.2 NORMALIZE_CTRL1 ................ 97

3.4.3 NORMALIZE_LEN_CTRL ....... 98

3.4.4 FRAM_ACK_CTRL0 .................. 98

3.4.5 FRAM_ACK_CTRL1 ................ 100

3.4.6 WIN_RULE_CTRL0 ................. 101

3.4.7 WIN_RULE_CTRL1 ................. 101

3.4.8 WIN_RULE_CTRL2 ................. 102

3.4.9 WIN_RULE_CTRL3 ................. 103

3.4.10 WIN_RULE_CTRL4 ................. 103

3.4.11 WIN_RULE_CTRL5 ................. 104

3.4.12 WIN_RULE_CTRL6 ................. 104

3.4.13 WIN_RULE_CTRL7 ................. 105

3.4.14 WIN_RULE_CTRL8 ................. 105

3.4.15 WIN_RULE_CTRL9 ................. 106

3.4.16 WIN_RULE_CTRL10 ............... 106

3.4.17 WIN_RULE_CTRL11 ............... 107

3.4.18 WIN_RULE_CTRL12 ............... 107

3.4.19 WIN_RULE_CTRL13 ............... 108

3.4.20 TRUNK_HASH_EN ................. 108

3.5 ACL REGISTER (Address Range: 0x0400 ~

0x0454) 109

3.5.1 ACL_FUNC0 ............................. 109

3.5.2 ACL_FUNC1 ............................. 109

3.5.3 ACL_FUNC2 ............................. 110

3.5.4 ACL_FUNC3 ............................. 110

3.5.5 ACL_FUNC4 ............................. 110

3.5.6 ACL_FUNC5 ............................. 111

3.5.7 PRIVATE_IP_CTRL ................. 111

3.5.8 PORT0_VLAN_CTRL0 ............ 111

3.5.9 PORT0_VLAN_CTRL1 ............ 112

3.5.10 PORT1_VLAN_CTRL0 ............ 113

3.5.11 PORT1_VLAN_CTRL1 ............ 114

3.5.12 PORT2_VLAN_CTRL0 ............ 115

3.5.13 PORT2_VLAN_CTRL1 ............ 116

3.5.14 PORT3_VLAN_CTRL0 ............ 116

3.5.15 PORT3_VLAN_CTRL1 ............ 117

3.5.16 PORT4_VLAN_CTRL0 ............ 118

Atheros Communications, Inc. AR8327/AR8327N Seven-port Gigabit Ethernet Switch • 5

COMPANY CONFIDENTIAL June 2011 • 5

3.5.17 PORT4_VLAN_CTRL1 ............ 119

3.5.18 PORT5_VLAN_CTRL0 ............ 119

3.5.19 PORT5_VLAN_CTRL1 ............ 120

3.5.20 PORT6_VLAN_CTRL0 ............ 121

3.5.21 PORT6_VLAN_CTRL1 ............ 122

3.5.22 IPv6 Private Base Address Register

0 ................................................... 122

3.5.23 IPv6 Private Base Address Register

1 ................................................... 123

3.5.24 IPv6 Private Base Address Register

2 ................................................... 123

3.6 LOOKUP REGISTER (Address Range:

0x0600 ~ 0x0708) 124

3.6.1 ATU_DATA0 ............................. 125

3.6.2 ATU_DATA1 ............................. 125

3.6.3 ATU_DATA2 ............................. 126

3.6.4 ATU_FUNC_REG ..................... 126

3.6.5 VTU_FUNC_REG0 ................... 128

3.6.6 VTU_FUNC_REG1 ................... 129

3.6.7 ARL_CTRL ................................ 130

3.6.8 GLOBAL_FW_CTRL0 .............. 131

3.6.9 GLOBAL_FW_CTRL1 .............. 133

3.6.10 GOL_LEARN_LIMIT ............... 133

3.6.11 TOS_PRI_MAP_REG0 ............. 134

3.6.12 TOS_PRI_MAP_REG1 ............. 135

3.6.13 TOS_PRI_MAP_REG2 ............. 135

3.6.14 TOS_PRI_MAP_REG3 ............. 136

3.6.15 TOS_PRI_MAP_REG4 ............. 136

3.6.16 TOS_PRI_MAP_REG5 ............. 137

3.6.17 TOS_PRI_MAP_REG6 ............. 137

3.6.18 TOS_PRI_MAP_REG7 ............. 138

3.6.19 VLAN_PRI_MAP_REG0 ......... 138

3.6.20 LOOP_CHECK_RESULT ........ 139

3.6.21 PORT0_LOOKUP_CTRL ......... 139

3.6.22 PORT0_PRI_CTRL .................... 142

3.6.23 PORT0_LEARN_LIMIT ........... 143

3.6.24 PORT1_LOOKUP_CTRL ......... 144

3.6.25 PORT1_PRI_CTRL Address 0x0670

147

3.6.26 PORT1_LEARN_LIMIT ........... 148

3.6.27 PORT2_LOOKUP_CTRL ......... 149

3.6.28 PORT2_PRI_CTRL .................... 151

3.6.29 PORT2_LEARN_LIMIT ........... 152

3.6.30 PORT3_LOOKUP_CTRL ......... 153

3.6.31 PORT3_PRI_CTRL .................... 156

3.6.32 PORT3_LEARN_LIMIT ........... 157

3.6.33 PORT4_LOOKUP_CTRL ......... 158

3.6.34 PORT4_PRI_CTRL ................... 160

3.6.35 PORT4_LEARN_LIMIT ........... 161

3.6.36 PORT5_LOOKUP_CTRL ......... 162

3.6.37 PORT5_PRI_CTRL ................... 165

3.6.38 PORT5_LEARN_LIMIT ........... 166

3.6.39 PORT6_LOOKUP_CTRL ......... 167

3.6.40 PORT6_PRI_CTRL ................... 170

3.6.41 PORT6_LEARN_LIMIT ........... 171

3.6.42 GOL_TRUNK_CTRL0 ............. 172

3.6.43 GOL_TRUNK_CTRL1 ............. 173

3.6.44 GOL_TRUNK_CTRL2 ............. 174

3.7 QM REGISTER(BASE ADDR:0x0800) 175

3.7.1 GLOBAL_FLOW_THD ........... 180

3.7.2 QM_CTRL_REG ....................... 180

3.7.3 WAN_QUEUE_MAP_REG ..... 182

3.7.4 LAN_QUEUE_MAP_REG ...... 183

3.7.5 PORT0_WRR_CTRL ................ 184

3.7.6 PORT1_WRR_CTRL ................ 185

3.7.7 PORT2_WRR_CTRL ................ 185

3.7.8 PORT3_WRR_CTRL ................ 186

3.7.9 PORT4_WRR_CTRL ................ 187

3.7.10 PORT5_WRR_CTRL ................ 188

3.7.11 PORT6_WRR_CTRL ................ 189

3.7.12 PORT0_EG_RATE_CTRL0 ...... 190

3.7.13 PORT0_EG_RATE_CTRL1 ...... 191

3.7.14 PORT0_EG_RATE_CTRL2 ...... 192

3.7.15 PORT0_EG_RATE_CTRL3 ...... 192

3.7.16 PORT0_EG_RATE_CTRL4 ...... 193

3.7.17 PORT0_EG_RATE_CTRL5 ...... 194

3.7.18 PORT0_EG_RATE_CTRL6 ...... 194

3.7.19 PORT0_EG_RATE_CTRL7 ...... 198

3.7.20 PORT1_EG_RATE_CTRL0 ...... 202

3.7.21 PORT1_EG_RATE_CTRL0 ...... 203

3.7.22 PORT1_EG_RATE_CTRL3 ...... 203

3.7.23 PORT1_EG_RATE_CTRL0 ...... 204

3.7.24 PORT1_EG_RATE_CTRL6 ...... 205

3.7.25 PORT1_EG_RATE_CTRL7 ...... 206

3.7.26 PORT2_EG_RATE_CTRL0 ...... 207

3.7.27 PORT2_EG_RATE_CTRL0 ...... 208

3.7.28 PORT2_EG_RATE_CTRL0 ...... 208

3.7.29 PORT2_EG_RATE_CTRL0 ...... 209

3.7.30 PORT2_EG_RATE_CTRL0 ...... 210

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AR8327手册

AR8327参考资料

AR8327_AR8328(N) Design Guide

AR8327 Demo资料

DB120参考板资料 AR9344+AR8327+AR9380

AR9344 datasheet

Atheros AR2317手册

TP-LINK TL-WN823N无线USB网卡驱动 for macOS10.15 (Catalina)

NIS-Elements AR快速手册.pdf

AR9582数据手册

AR9331文档手册路由器芯片手册

AR8031数据手册

sharp ar158维修手册

华为AR系列交换机配置手册

phy芯片AR8035芯片手册

AR.Drone开发手册

AR9341原理图和手册

夏普 AR-2048 2348 维修手册

ar0134 寄存器参考手册

AR0130数据手册

高通AR9287 wifi芯片数据手册

H3C AR18 21a 手册

夏普 ar 2648n复印机手册

夏普AR4821D使用手册

HBR机器人AR语言手册.pdf

威纶AR60T_AR80iL-O系列通用变频器使用手册.pdf

夏普数码多功能复合机AR-M620N AR-M700N维修手册.pdf

Presonus普瑞声纳StudioLive_ AR 系列用户手册.pdf

AR8033 datasheet

AR6103数据手册

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