QuartusII时序约束方法

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QuartusII时序约束方法,Quartus II 系列资料,包括常用的sdc命令和约束的方法
Time Quest Agenda a Introduction to Time Quest a I meQuest terminology review a Using TimeQuest a EXample Application @2007 Altera Corporation--Confidential Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation AAUBRA Time Quest Timing Analyzer New timing engine in Quartus ll a Provide timing analysis solution o Quartes Static Timing Analyzer Tool-D /qto/quartus/eesigsskchiptriplchiptrip-cycleneifchiptrip-chiptrip 回叉 BEw度 Coren Fewe sot Ht clocks sumary meeting requirements of all Dod Mca:o: (d with l ■d2A0542512 c 400000m20 H Slad Hulcgam(ckz c4600 Ood. Sunup users O-d Tramcar l Slad Hako m(cell slck Histogram(ok2) FPGA design background 10 25 ASIC design background y Led sDC Fin OstelndhidwlConher b Unan Neliel Easy-to-use interface 中 P Made Sunney Repot H OrnSurmeyReorr y Bmade Cbkt SunmwvReoc 习0 noCks Sune Rep p GetMe Cbk Ttmtets epcr Standard reporting& constraint Repet Net Tno terminology Cease slack Hogan y Info: Reall ng soc File: chI trip. sta. sdc Scripting emphasis ds updata_tirm ne_ne1i时t ldt treats_ti m ng-murmary -pa ld creat_l ack_hinbogran -urbina n clk2 ld, repcrt-stocka -panel."clocks Ids report-clock transfers -panel ene Clork Transfers"; Irds create slack histogra -numbing 30 -clock nane clkI . A Ce S HaD, ges門 厂NM @2007 Altera Corporation--Confidential Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation AAUBRA Time Quest Timing Analyzer(cont) More accurate analysis rise/fall delays o Quartes Static Timing Analyzer Tool-D /qto/quartus/eesigsskchiptriplchiptrip-cycleneifchiptrip-chiptrip 回叉 BEw度 Coren Fewe sot Ht clocks sumary SDC Support Dod Mca:o: (d with l ■d2A0542512 c 400000m20 H Slad Hulcgam(ckz c4600 More advanced standardized Ood. Sunup O-d Tramcar l Slad Hako m(cell slck Histogram(ok2) constraint methodology 10 Easily supports more complex y Led sDC Fin 25 OstelndhidwlConher designs and analysis b Unan Neliel 御日ct 中 P Made Sunney Repot 615 H OrnSurmeyl e Complex clocking schemes y Bmade Cbkt SunmwvReoc 习0 noCks Sune Rep p GetMe Cbk Ttmtets epcr e Source-synchronous designs Repet Net Tno y Info: Reall ng soc File: chI trip. sta. sdc ds updata_tirm ne_ne1i时t ldt treats_ti m ng-murmary -pa ld creat_l ack_hinbogran -urbina n clk2 ld, repcrt-stocka -panel."clocks Ids report-clock transfers -panel ene Clork Transfers"; Irds create slack histogra -numbing 30 -clock nane clkI . A Ce S HaD, ges門 厂NM @2007 Altera Corporation--Confidential Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation AAUBRA ATERA Validating Performance with the TimeQuest Static Timing Analyzer Ti ImeQuest /erminology Revlew @2007 Altera Corporation-Confidential Time Quest Terminology Review a Launch latch edges Arrival time vs required time Setup hold analysis Slack a sDC terminology @2007 Altera Corporation--Confidential Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation AAUBRA Path& Analysis Types Async Path PRE Data Path PRE CLR CLR Clock Paths Async Path Three types of Paths Two types of Analysis Clock Paths Synchronous -clock data paths 2 Data Path 2. Asynchronous* -clock async paths Asynchronous Paths Asynchronous refers to signals feeding the asynchronous control ports of the registers @2007 Altera Corporation--Confidential Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and Mega Core are trademarks of Altera Corporation AAUBRA Setup Hold DATA PRE CLK Q su CLK CLR DATA X Valid X Setup The minimum time data signal must be stable BEFORE clock edge Hold The minimum time data signal must be stable AFTER clock edge ogether, the setup time and hold time form a Data Required window, the time around a clock edge in which data must be stable. @2007 Altera Corporation--Confidential Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and Mega Core are trademarks of Altera Corporation AAUBRA Launch Latch Edges REG1 REG2 Comb ogIC CLR CLR CLK Latch Launch Edge Edge CLK DATA Data valid Launch edge the edge which "launches" the data from source register Latch Edge the edge which latches" the data at destination register (with respect to the launch edge, typically 1 cycle @2007 Altera Corporation--Confidential Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and Mega Core are trademarks of Altera Corporation AAUBRA 10

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