1
Features
• Low-voltage and Standard-voltage Operation
– 1.8 (V
CC
= 1.8V to 3.6V)
• Internally Organized 65,536 x 8
• Two-wire Serial Interface
• Schmitt Triggers, Filtered Inputs for Noise Suppression
• Bidirectional Data Transfer Protocol
• 1 MHz (3.6V), 400 kHz (1.8V) Compatibility
• Write Protect Pin for Hardware and Software Data Protection
• 128-byte Page Write Mode (Partial Page Writes Allowed)
• Self-timed Write Cycle (5 ms Max)
• High Reliability
– Endurance: 1,000,000 Write Cycles
– Data Retention: 40 Years
• Lead-free/Halogen-free Devices Available
• 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead TSSOP,
8-lead LAP and 8-lead SAP Packages
• Die Sales: Wafer Form, Waffle Pack and Bumped Die
Description
The AT24C512B provides 524,288 bits of serial electrically erasable and programma-
ble read only memory (EEPROM) organized as 65,536 words of 8 bits each. The
device’s cascadable feature allows up to four devices to share a common two-wire
bus. The device is optimized for use in many industrial and commercial applications
where low-power and low-voltage operation are essential. The devices are available in
space-saving 8-pin PDIP, 8-lead JEDEC SOIC, 8-lead TSSOP, 8-lead Leadless Array
(LAP), and 8-lead SAP packages. In addition, the entire family is available in a 1.8V
(1.8V to 3.6V) version.
Table 1. Pin Configurations
Pin Name Function
A0–A2 Address Inputs
SDA Serial Data
SCL Serial Clock Input
WP Write Protect
NC No Connect
Rev. 5112A–SEEPR–8/05
Two-wire Serial
EEPROM
512K (65,536 x 8)
AT24C512B
with Three Device
Address Inputs
Preliminary
8-lead PDIP
1
2
3
4
8
7
6
5
A0
A1
A2
GND
VCC
WP
SCL
SDA
8-lead Leadless Array
Bottom View
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
A0
A1
A2
GND
8-lead TSSOP
1
2
3
4
8
7
6
5
A0
A1
A2
GND
VCC
WP
SCL
SDA
8-lead SAP
Bottom View
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
A0
A1
A2
GND
8-lead SOIC
1
2
3
4
8
7
6
5
A0
A1
A2
GND
VCC
WP
SCL
SDA
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