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INVENTIVE
CONFIDENTIAL
Formal Verification Guide
Prototype | Implement | Verify
August 6, 2009 Cadence Confidential
2
Agenda
• Equivalence Checking Refresh
• Verification Guide
– RTL Design
– Verifiable Synthesis Flow
– Abort Resolution
• ECO Automation
• Best Practice Recommendation
August 6, 2009 Cadence Confidential
3
August 6, 2009 Cadence Confidential
3
August 6, 2009 Cadence Confidential
3
ECO
Implementation
o1
o2
Provides automated
RTL2GDS ECO solution
Identifies and generates
fix to implement ECO
Interfaces with physical
implementation tool flow
Encounter Conformal Product Family
Verifies 100% of design
functionality without
requiring test vectors
Provides independent
verification for lowest risk
silicon
Digital Custom Verification
including Memories, Data
Paths, and IO
Orders of magnitude faster
than simulation
Equivalence
Checking
RTL
or
Gate
RTL
or
Gate
Functional
Checks
Finds bugs earlier in
the design cycle
Verifies proper CDC
synchronization to
avoid clock related
re-spins
Creates safer EC
environment
Constraint
Design
Validation, generation
and analysis of
constraints
Uses industry proven
formal engines
Shorter design cycle
with improved timing
constraints
Low Power
Verification
Validates CPF
LP Equivalence
Checking
Verifies Low
Power design
implementation
Performs
structural and
functional checks
A B
v1
v2
ISO
Functional
Checks
August 6, 2009 Cadence Confidential
4
August 6, 2009 Cadence Confidential
4
August 6, 2009 Cadence Confidential
4
ECO
Implementation
o
1
o
2
Automated RTL2GDS ECO solution
Identifies and generates ECO fix
Encounter Conformal & FED Product Family
100% Independent vector-less
verification of implementation
RTL
Gate
Transistor
CDC & Ext Checks
Equivalence
Checking
RTL
or
Gate
RTL
or
Gate
Constraint
Design
Validation, generation & analysis
of constraints
Shorter design cycles with
improved timing constraints
Low Power
Verification
Structural and functional LP checks
LP design implementation
Verification
LP Equivalence Checking
A B
v
1
v2
ISO
Architectural & Economic Forecasting
Lower IC Cost & Expedite TTM
Chip Planning
Systems
New Products
New Products
RC-Physical
Synthesis
Physical Correlation &
Predictability with final
backend
Congestion Analysis & Opto
(Congestion Relief)
INVENTIVE
CONFIDENTIAL
Crash Course on
Equivalency Checking
Prototype | Implement | Verify
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