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MC145170–1MOTOROLA
1
Advance Information
! !"
CMOS
The new MC145170–1 is pin–for–pin compatible with the MC145170. A
comparison of the two parts is shown in the table below. The MC145170–1 is
recommended for new designs.
The MC145170–1 is a single–chip synthesizer capable of direct usage in the
MF, HF, and VHF bands. A special architecture makes this PLL the easiest to
program in the industry. Either a bit– or byte–oriented format may be used. Due
to the patented BitGrabber registers, no address/steering bits are required for
random access
of the three registers. Thus, tuning can be accomplished via a
2–byte serial transfer to the 16–bit N register.
The device features fully programmable R and N counters, an amplifier at the
f
in
pin, on–chip support of an external crystal, a programmable reference
output, and both single– and double–ended phase detectors with linear transfer
functions (no dead zones). A configuration (C) register allows the part to be
configured to meet various applications. A patented feature allows the C
register to shut off unused outputs, thereby minimizing noise and interference.
In order to reduce lock times and prevent erroneous data from being loaded
into the counters, a patented jam–load feature is included. Whenever a new
divide ratio is loaded into the N register, both the N and R counters are
jam–loaded with their respective values and begin counting down together. The
phase detectors are also initialized during the jam load.
• Operating Voltage Range: 2.5 to 5.5 V
• Maximum Operating Frequency:
185 MHz @ V
in
= 500 mV p–p, 4.5 V Minimum Supply
100 MHz @ V
in
= 500 mV p–p, 3.0 V Minimum Supply
• Operating Supply Current: 0.6 mA @ 3 V, 30 MHz
1.5 mA @ 3 V, 100 MHz
3.0 mA @ 5 V, 50 MHz
5.8 mA @ 5 V, 185 MHz
• Operating Temperature Range: – 40 to 85°C
• R Counter Division Range: 1 and 5 to 32,767
• N Counter Division Range: 40 to 65,535
• Direct Interface to Motorola SPI and National MICROWIRE Serial Data
Ports
• Chip Complexity: 4800 FETs or 1200 Equivalent Gates
• See Application Note AN1207/D
COMPARISION OF THE PLL FREQUENCY SYNTHESIZERS
Parameter MC145170–1 MC145170
Technology 1.2 µm CMOS 1.5 µm CMOS
Maximum Frequency with 5 V ± 10% Supply, f
in
185 MHz 160 MHz
Maximum Frequency with 5 V ± 10% Supply, OSC
in
25 MHz 20 MHz
Maximum Supply Voltage 5.5 V 6.0 V
Maximum Input Capacitance, f
in
7 pF 5 pF
This document contains information on a new product. Specifications and information herein are subject to change without notice.
BitGrabber is a trademark of Motorola Inc. MICROWIRE is a trademark of National Semiconductor Corp.
Order this document
by MC145170–1/D
SEMICONDUCTOR TECHNICAL DATA
f
R
LD
V
SS
9
10
11
12
φ
V
V
DD
PD
out
8
7
6
5
4
3
2
1
D
out
CLK
ENB
f
in
REF
out
OSC
out
OSC
in
14
15
16
PIN ASSIGNMENT
D
in
f
V
P SUFFIX
PLASTIC DIP
CASE 648
D SUFFIX
SOG PACKAGE
CASE 751B
ORDERING INFORMATION
MC145170P1 Plastic DIP
MC145170D1 SOG Package
MC145170DT1 TSSOP
φ
R
16
1
13
DT SUFFIX
TSSOP
CASE 948C
16
1
16
1
Motorola, Inc. 1996
REV 1
3/96
![](https://csdnimg.cn/release/download_crawler_static/1623771/bg2.jpg)
MC145170–1 MOTOROLA
2
BLOCK DIAGRAM
ENB
OSC
in
D
in
CLK
OSC
out
f
in
OSC
1
2
7
5
4
INPUT
AMP
3
15
16
15–STAGE R COUNTER
16–STAGE N COUNTER
SHIFT
REGISTER
AND
CONTROL
LOGIC
POR
BitGrabber N REGISTER
16 BITS
BitGrabber C REGISTER
8 BITS
BitGrabber R REGISTER
15 BITS
PHASE/FREQUENCY
DETECTOR B AND CONTROL
PHASE/FREQUENCY
DETECTOR A AND CONTROL
LOCK DETECTOR
AND CONTROL
16
LD
PD
out
φ
R
φ
V
10
15
14
13
11
9
PIN 16 = V
DD
PIN 12 = V
SS
6
4–STAGE
REFERENCE
DIVIDER
REF
out
3
D
out
8
f
V
CONTROL
f
R
CONTROL
f
R
f
V
MAXIMUM RATINGS* (Voltages Referenced to V
SS
)
Symbol
Parameter Value Unit
V
DD
DC Supply Voltage – 0.5 to + 5.5 V
V
in
DC Input Voltage – 0.5 to V
DD
+ 0.5 V
V
out
DC Output Voltage – 0.5 to V
DD
+ 0.5 V
I
in
DC Input Current, per Pin ± 10 mA
I
out
DC Output Current, per Pin ± 20 mA
I
DD
DC Supply Current, V
DD
and V
SS
Pins ± 30 mA
P
D
Power Dissipation, per Package 300 mW
T
stg
Storage Temperature – 65 to + 150 °C
T
L
Lead Temperature, 1 mm from Case
for 10 seconds
260 °C
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the limits in the Electrical Characteristics
tables or Pin Descriptions section.
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, pre-
cautions must be taken to avoid applications of
any voltage higher than maximum rated volt-
ages to this high–impedance circuit. For proper
operation, V
in
and V
out
should be constrained
to the range V
SS
≤ (V
in
or V
out
) ≤ V
DD
.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either V
SS
or V
DD
). Unused outputs must be left open.
![](https://csdnimg.cn/release/download_crawler_static/1623771/bg3.jpg)
MC145170–1MOTOROLA
3
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
SS
, T
A
= – 40 to + 85°C)
Symbol
Parameter Test Condition
V
DD
V
Guaranteed
Limit
Unit
V
DD
Power Supply Voltage Range — 2.5 to 5.5 V
V
IL
Maximum Low–Level Input Voltage*
(D
in
, CLK, ENB
, f
in
)
dc Coupling to f
in
2.5
4.5
5.5
0.50
1.35
1.65
V
V
IH
Minimum High–Level Input Voltage*
(D
in
, CLK, ENB
, f
in
)
dc Coupling to f
in
2.5
4.5
5.5
2.00
3.15
3.85
V
V
Hys
Minimum Hysteresis Voltage (CLK, ENB) 2.5
5.5
0.15
0.20
V
V
OL
Maximum Low–Level Output Voltage
(Any Output)
I
out
= 20 µA 2.5
5.5
0.1
0.1
V
V
OH
Minimum High–Level Output Voltage
(Any Output)
I
out
= – 20 µA 2.5
5.5
2.4
5.4
V
I
OL
Minimum Low–Level Output Current
(PD
out
, REF
out
, f
R
, f
V
, LD, φ
R
, φ
V
)
V
out
= 0.3 V
V
out
= 0.4 V
V
out
= 0.5 V
2.5
4.5
5.5
0.12
0.36
0.36
mA
I
OH
Minimum High–Level Output Current
(PD
out
, REF
out
, f
R
, f
V
, LD, φ
R
, φ
V
)
V
out
= 2.2 V
V
out
= 4.1 V
V
out
= 5.0 V
2.5
4.5
5.5
– 0.12
– 0.36
– 0.36
mA
I
OL
Minimum Low–Level Output Current
(D
out
)
V
out
= 0.4 V 4.5 1.6 mA
I
OH
Minimum High–Level Output Current
(D
out
)
V
out
= 4.1 V 4.5 – 1.6 mA
I
in
Maximum Input Leakage Current
(D
in
, CLK, ENB
, OSC
in
)
V
in
= V
DD
or V
SS
5.5 ± 1.0 µA
I
in
Maximum Input Current
(f
in
)
V
in
= V
DD
or V
SS
5.5 ± 120 µA
I
OZ
Maximum Output Leakage Current (PD
out
) V
in
= V
DD
or V
SS
,
Output in High–Impedance State
5.5 ± 100 nA
(D
out
) 5.5 ± 5 µA
I
DD
Maximum Quiescent Supply Current V
in
= V
DD
or V
SS
; Outputs Open;
Excluding f
in
Amp Input Current Component
5.5 100 µA
I
dd
Maximum Operating Supply Current f
in
= 500 mV p–p;
OSC
in
= 1 MHz @ 1 V p–p;
LD, f
R
, f
V
, REF
out
= Inactive and No Connect;
OSC
out
, φ
V
, φ
R
, PD
out
= No Connect;
D
in
, ENB, CLK = V
DD
or V
SS
— ** mA
*When dc coupling to the OSC
in
pin is used, the pin must be driven rail–to–rail. In this case, OSC
out
should be floated.
**The nominal values at 3 V are 0.6 mA @ 30 MHz, and 1.5 mA @ 100 MHz. The nominal values at 5 V are 3.0 mA @ 50 MHz, and 5.8 mA
@ 185 MHz. These are not guaranteed limits.
![](https://csdnimg.cn/release/download_crawler_static/1623771/bg4.jpg)
MC145170–1 MOTOROLA
4
AC INTERFACE CHARACTERISTICS ( T
A
= – 40 to + 85°C, C
L
= 50 pF, Input t
r
= t
f
= 10 ns unless otherwise indicated)
Symbol
Parameter
Figure
No.
V
DD
V
Guaranteed
Limit
Unit
f
clk
Serial Data Clock Frequency (Note: Refer to Clock t
w
Below) 1 2.5
4.5
5.5
dc to 3.0
dc to 4.0
dc to 4.0
MHz
t
PLH
, t
PHL
Maximum Propagation Delay, CLK to D
out
1, 5 2.5
4.5
5.5
150
85
85
ns
t
PLZ
, t
PHZ
Maximum Disable Time, D
out
Active to High Impedance 2, 6 2.5
4.5
5.5
300
200
200
ns
t
PZL
, t
PZH
Access Time, D
out
High Impedance to Active 2, 6 2.5
4.5
5.5
0 to 200
0 to 100
0 to 100
ns
t
TLH
, t
THL
Maximum Output Transition Time, D
out
CL = 50 pF 1, 5 2.5
4.5
5.5
150
50
50
ns
CL = 200 pF 1, 5 2.5
4.5
5.5
900
150
150
ns
C
in
Maximum Input Capacitance – D
in
, ENB, CLK — 10 pF
C
out
Maximum Output Capacitance – D
out
— 10 pF
TIMING REQUIREMENTS ( T
A
= – 40 to + 85°C, Input t
r
= t
f
= 10 ns unless otherwise indicated)
Symbol
Parameter
Figure
No.
V
DD
V
Guaranteed
Limit
Unit
t
su
, t
h
Minimum Setup and Hold Times, D
in
vs CLK 3 2.5
4.5
5.5
55
40
40
ns
t
su
, t
h
, t
rec
Minimum Setup, Hold, and Recovery Times, ENB vs CLK 4 2.5
4.5
5.5
135
100
100
ns
t
w(H)
Minimum Inactive–High Pulse Width, ENB 4 2.5
4.5
5.5
400
300
300
ns
t
w
Minimum Pulse Width, CLK 1 2.5
4.5
5.5
166
125
125
ns
t
r
, t
f
Maximum Input Rise and Fall Times, CLK 1 2.5
4.5
5.5
100
100
100
µs
![](https://csdnimg.cn/release/download_crawler_static/1623771/bg5.jpg)
MC145170–1MOTOROLA
5
SWITCHING WAVEFORMS
10%
V
DD
V
SS
1/f
clk
D
out
CLK
90%
50%
90%
50%
10%
t
PLH
t
PHL
t
TLH
t
THL
t
w
t
w
t
f
t
r
Figure 1.
ENB
D
out
D
out
50%
V
DD
V
SS
50%
t
PZH
t
PZL
t
PLZ
50%
t
PHZ
Figure 2.
10%
90%
V
DD
V
SS
HIGH
IMPEDANCE
HIGH
IMPEDANCE
D
in
CLK
50%
VALID
50%
t
su
t
h
V
DD
V
SS
V
DD
V
SS
Figure 3.
CLK
ENB
50%
t
su
t
h
FIRST
CLK
LAST
CLK
t
rec
50%
Figure 4.
V
DD
V
SS
V
DD
V
SS
t
w(H)
TEST POINT
DEVICE
UNDER
TEST
C
L
*
* Includes all probe and fixture capacitance.
Figure 5. Test Circuit
TEST POINT
DEVICE
UNDER
TEST
C
L
*
* Includes all probe and fixture capacitance.
Figure 6. Test Circuit
7.5 k
Ω
CONNECT TO V
DD
WHEN TESTING t
PLZ
AND t
PZL
. CONNECT TO
V
SS
WHEN TESTING
t
PHZ
AND t
PZH
.
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