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CC3000

英文编程指南

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CC3000中英文编程指南及时序图.zip （10个子文件）

Chinese wiki

Host_to_CC3000__HCI_CMND_READ_BUFFER_SIZE.png 312KB

CC3000 主机编程指南.pdf 1010KB

CC3000 Host Driver Porting Guide 06152012.pdf 226KB

CC3000 Serial Port Interface (SPI) - Texas Instruments Wiki.pdf 2.18MB

CC3000 Basic Wi-Fi example application for MSP430 06152012.pdf 1.27MB

the_remaining_6_bytes.png 251KB

CC3000_to_Host__HCI_CMND_SIMPLE_LINK_START command complete.png 305KB

CC3000 Host Programming Guide - Texas Instruments Wiki.pdf 1.81MB

first_four_bytes.png 240KB

CC3000_to_Host - HCI_CMND_READ_BUFFER_SIZE command complete.png 344KB

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CC3000 Serial Port Interface (SPI)

From Texas Instruments Wiki

CC3000 Serial Port Interface (SPI)

Return to CC3000 Main Page

Return to Host Programming guide

Contents

1 CC3000 Serial Port Interface

1.1 Overview

1.2 Protocol Description

1.2.1 Master Write Transaction

1.2.1.1 Master Write Transaction Header

1.2.1.2 First Host Write Operation

1.2.1.3 Generic Host Write Operation

1.2.2 Master Read Transaction

1.2.2.1 Master Read Transaction Header

1.3 Example Implementation of SPI

1.3.1 Busy Waiting SPI Implementation

1.3.1.1 Write operation

1.3.1.2 Read operation

1.3.2 DMA based SPI implementation

1.3.2.1 Write operation

1.3.2.2 Read operation

1.4 CC3000 Init Operation

1.4.1 1. Host ->> CC3000 - HCI_CMND_SIMPLE_LINK_START

1.4.2 2. CC3000 ->> Host - HCI_CMND_SIMPLE_LINK_START command complete

1.4.3 3. Host ->> CC3000 - HCI_CMND_READ_BUFFER_SIZE

1.4.4 4. CC3000 ->> Host - HCI_CMND_READ_BUFFER_SIZE command complete

2 Related Pages

CC3000 Serial Port Interface

Overview

The SPI is based on the five-line, master/slave communication model as shown in the following figure:

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Masterslave communication model.jpg

The lines are described as follows:

I/O Description

CLCK

(1)

Clock (~0 to 16 MHz) from host to slave

nCS

(2)

nCS (active low) signal from host to slave

MOSI

Data from host to slave

IRQ

(3)

Interrupt from slave to host

MISO Data from slave to host

(1)

CLCK provides a clock to the SPI interface on the CC3000 device.

(2)

nCS selects a CC3000 device, indicating that a master wants to communicate to the CC3000 device.

(3)

IRQ is a dual-purpose slave to the master direction line: in SPI IDLE state while no data transfer is active, driving IRQ low indicates to the master that the CC3000 device has data to

pass to it; driving IRQ low following nCS deassertion indicates that the CC3000 device is ready to receive data. All behaviors are explained in detail in the following sections.

Protocol Description

The SPI protocol is used to communicate with the CC3000 device from the host MCU that is acting as the SPI master while the CC3000 device is the SPI slave. The protocol is an extension of the

existing standard SPI. The endianness on transport is assumed to be most-significant bit (MSB) first.

The clock and phase settings for the SPI are configured such that the data is sampled on the falling edge of the clock cycle. Note that different MCU may use different naming conventions in order

to configure SPI clock phase and polarity, For example, MSP430 uses UCCKPL and UCCKPH for clock polarity and phase respectively. Both are set to 0, indicating that the data is sampled on the

falling edge of the clock cycle. The more generic convention is CPOL and CPHA, however, in order to configure sampling on the falling edge of the clock cycle, CPHA is set to 1.

All data sent or received over the SPI interface must be 16-bit aligned. A padding byte is added where required. Each packet passing on the SPI bus consists of a 5-byte SPI header followed by user

data and optionally by a padding byte so that the whole length is 16-bit aligned, as shown in the next Figure.

The first byte of the header is an operation opcode (READ or WRITE) followed by two bytes that indicate the size of the payload length (including the alignment byte). Two busy bytes then follow to

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conclude the header.

The data payload directly follows the last byte of the header. The padding byte is added when the length of the payload part of the packet is even.

Master Write Transaction

There is a slight difference between the first master write transaction after power up and the rest of the write transactions. The difference follows from the internal CC3000 implementation of

SPI.

Ma s te r W ri t e T r a ns a c t i o n H e a d er

The header precedes each data packet. The structure of the header (see figure below) is independent of whether or not it is a first write transaction.

The first byte of the header is the write opcode followed by two bytes that indicate the size of the payload length (including the alignment byte). Two busy bytes then follow to conclude the

header.

The data payload directly follows the last byte of the header. The following summarizes the header structure:

Write = Opcode for write is 0x01

M<sub>MSB</sub>, M<sub>LSB</sub> = 16-bit data payload length (including alignment byte)

Busy = Busy byte (0x00)

Fi r st H o st W r i t e O p e r a t i on

The first write transaction to occur after release of the shutdown has slightly different timing than the others.

The normal Master SPI write sequence is nCS low, followed by IRQ low (CC3000 host), indicating that the CC3000 core device is ready to accept data. However, after power up the sequence is slightly

different, as shown in the following Figure:

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The following is a sequence of operations:

1. The master detects the IRQ line low: in this case the detection of IRQ low does not indicate the intention of the CC3000 device to communicate with the master but rather CC3000 readiness

after power up.

2. The master asserts nCS.

3. The master introduces a delay of at least 50 μs before starting actual transmission of data.

4. The master transmits the first 4 bytes of the SPI header.

5. The master introduces a delay of at least an additional 50 μs.

6. The master transmits the rest of the packet.

Ge n er i c Ho s t W r i te O p e r a ti o n

1. The master asserts nCS (that is, drives the signal low) and waits for IRQ assertion.

2. The CC3000 device asserts IRQ when ready to receive the data.

3. The master starts the write transaction. The write transaction consists of a 5-byte header followed by the payload and a padding byte (if required: remember, the total packet length must be

16-bit aligned)

4. After the last byte of data, the nCS is deasserted by the master.

5. The CC3000 device deasserts the IRQ line.

The following figure shows a master write transaction.

Master Read Transaction

The master read transaction is initiated by the CC3000 device by asserting (that is, driving low) an IRQ line while the bus is in IDLE state. If a master detects an IRQ assertion while in the

process of initialization of the master write transaction, it is up to the master to resolve the order of read and write operations. If the master continues with the master write transaction, the

deasserted IRQ can be treated as a deassertion that is required as a response to nCS. The following is a sequence:

1. The IRQ line is asserted by the CC3000 device.

2. The master asserts the nCS line.

3. The master transmits the following 3 bytes: read opcode followed by two busy bytes.

4. The CC3000 sends back the following data: the first two bytes indicate the payload length and the data payload bytes follow, immediately after.

5. At the end of read transaction, the master drives nCS inactive.

6. The CC3000 device deasserts an IRQ line.

The following figure shows the master read transaction process.

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Ma s te r R ea d T r a n sa c t i o n He a d e r

The following summarizes the master read transaction header structure:

Read = Opcode for write is 0x03

SMSB, SLSB = 16-bit data payload length (including alignment byte)

Busy = Busy byte (0x00)

Example Implementation of SPI

The following two sections present two example implementations of the CC3000 SPI interface in terms of state-machines. The first implementation is based on the MSP430, which does not use DMA

during read/write operations (also called the busy waiting approach) and thus the state-machine is much easier but more MCU tight. The second implementation is based on the LM3S9B96 Stellaris,

which uses DMA for data transfer to or from the SPI.