Nov. 7, 2022 Page 5 of 192 Rev 1.00
AN7012
21.1
DDR3/DDR3L Schematic Implementation .........................................................................143
21.1.1
Two DDR3/DDR3L Chips Topology ................................................................................ 143
21.1.2
One DDR3/DDR3L Chips Topology ................................................................................ 144
21.1.3
Control Signals.................................................................................................................... 145
21.1.4
Power Supply and Reference Voltages .......................................................................... 145
21.2
PCB Design Considerations ..............................................................................................146
21.2.1
Trace Isolation Distance .................................................................................................... 146
21.2.2
Length Equalization ............................................................................................................ 148
21.2.3
Impedance ........................................................................................................................... 148
21.2.4
Layer Allocation for 8-layer Boards .................................................................................. 148
21.2.5
MV
DD
Power Plane Specification...................................................................................... 149
21.2.6
Types of Decoupling Capacitors ...................................................................................... 150
21.2.7
Minimizing Connection Inductance with HF Capacitors of Decoupling Capacitors .. 151
21.2.8
Placing Capacitors on the Top Layer .............................................................................. 151
21.2.9
Placing Capacitors on the Bottom Layer ........................................................................ 151
21.3
DDR3 PCB Layout Guide ....................................................................................................152
21.3.1
General Layout Rules ........................................................................................................ 152
21.3.2
Data Group Layout Rules .................................................................................................. 153
21.3.3
Clock Group Layout Rules ................................................................................................ 153
21.3.4
Address/Command Group Layout Rules ........................................................................ 154
21.3.5
Control Group Layout Rules ............................................................................................. 154
21.3.6
Length Difference Between Groups ................................................................................ 155
21.3.7
Skew Control ....................................................................................................................... 155
21.3.8
Reference Voltage .............................................................................................................. 155
21.3.9
MV
DD
/V
DD
/V
DDQ
Power Plane ............................................................................................ 156
22 ESD PROTECTION CIRCUIT EXAMPLE FOR GPIO ......................................... 157
23 REFERENCE SCHEMATICS ..................................................................................... 159
23.1
System Block .......................................................................................................................159
23.2
PMIC_DA9062 ......................................................................................................................160
23.3
VDDIO0/2/4/5 ........................................................................................................................161
23.4
VDDIO1 .................................................................................................................................162
23.5
eMMC1 (VDDIO3) .................................................................................................................163
23.6
VDDIO6/7/ADC/USB ............................................................................................................164
23.7
RGMII0_RTL8211F(D)I (VDDIO8) ........................................................................................165
23.8
RGMII1_RTL8211F(D)I (VDDIO9) ........................................................................................166
23.9
DDR3L ..................................................................................................................................167
23.10
Power ............................................................................................................................168
23.11
SOM Connectors ..........................................................................................................169
23.12
Power-on Setting and NAND Flash ............................................................................170
23.13
SD0 ................................................................................................................................171
