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© November 2009 Altera Corporation Quartus II Handbook Version 9.1 Volume 5: Embedded Peripherals
13. Avalon-ST Single Clock and Dual
Clock FIFO Cores
Core Overview
The Avalon
®
Streaming (Avalon-ST) Single Clock and Avalon-ST Dual Clock FIFO
cores are FIFO buffers which operate with a single clock and separate clocks for input
and output ports, respectively. You can configure the cores to include Avalon
Memory-Mapped (Avalon-MM) status interfaces to report the FIFO fill level.
The Avalon-ST Single Clock and Avalon-ST Dual Clock FIFO cores are SOPC
Builder-ready and integrates easily into any SOPC Builder-generated systems.
This chapter contains the following sections:
■ “Functional Description”
■ “Instantiating the Core in SOPC Builder” on page 13–3
■ “Device Support” on page 13–3
■ “Software Programming Model” on page 13–4
Functional Description
Figure 13–1 and Figure 13–2 show block diagrams of the Avalon-ST Single Clock and
Avalon-ST Dual Clock FIFO cores.
Figure 13–1. Avalon-ST Single Clock FIFO Core
Avalon-ST
Single-Clock
FIFO
Avalon-MM
Status
data_out
data_in
Avalon-ST
Sink
Avalon-ST
Source
QII55014-9.1.0
资源评论
- 黎明之星2016-08-09不错,挺详细的
- mjoly2262015-04-20对学习avalon st流接口很有参考价值
- chenlin19212012-12-17这个不错,挺详细的
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