关于Avalon-ST Single Clock FIFO比较全的资料qsys
这里面是关于qsys中元器件的介绍的，找了好多资料，发现这里面对于Avalon-ST Single Clock FIFO的介绍稍微详细一些；
Q51025 2014.0630 Avalon-MM Clock Crossing Bridge 10-3 Avalon-MM Clock Crossing Bridge The Avalon-MM Clock Crossing Bridge transfers Avalon- MM commands and responses between different clock domains. You can also use the Avalon-MM Clock Crossing Bridge between AXI masters and slaves of different clock domains The Avalon-MM Clock Crossing Bridge uses asynchronous FIFOs to implement clock crossing logic. The bridge parameters control the depth of the command and response fifos in both the master and slave clock domains. If the number of active reads exceeds the depth of the response FIfo, the Clock Crossing bridge stops sending reads To maintain throughput for high-performance applications, increase the response Fifo depth from the default minimum depth, which is twice the maximum burst size Related information Creating a System with Qsys Avalon-MM Clock Crossing Bridge Example In this example, the Avalon- MM Clock Crossing bridges separate slave components into two groups. Low- performance slave components are placed behind a single bridge and are clocked at a low speed. High performance components are placed behind a second bridge and are clocked at a higher speed By inserting clock-crossing bridges, you optimize the qsys interconnect and allow the Quartus Il Fitter to optimize paths that require minimal propagation delay Qsys System Design Components era corporation Send Feedback 10-4 Avalon-MM Clock Crossing Bridge Parameters Q11025 2014.06.30 Figure 10-3: Avalon-MM Clock Crossing Bridge Avalon-MM Clock-CI Clock-Cr Bridge Avalon Tristate JTAG Debug System ID Seven Segment Nodule Disp Brd Flash ry DDR Avalon-MM Master Port External SRAM Avalon-MM Clock Crossing Bridge Parameters Table 10-1: Avalon-MM Clock Crossing bridge Parameters Parameters Valu Description Data width 8, 16, 32, 64, Determines the data width of the 128, 256, 512, interfaces on the bridge, and affects the 1024(bits) size of both Fifos. For the highest bandwidth, set data width to be as wide as the widest master that connects to the bridg Altera Corporation Qsys System Design Components Send feedback Q51025 2014.0630 Avalon-MM Pipeline Bridge 10-5 Parameters Values Description Symbol width 1,2,, 32, Number of bits per symbol. For 64(bits) example, byte-oriented interfaces have 8-bit symbols Address width 1-32(bits) The address bits needed to address the downstream slaves Use automatically-determined address width The minimum bridge address width that is required to address the downstream slaves Maximum burst size 1,2,4,8, 16, 32, Determines the maximum length of 64, 128,256, bursts that the bridge supports 512,1024(bits) Command Fifo depth 2,4,8,16, 32, Command(master-to-slave)FIFO 64128,256,dept 512,10242048, 4096,8192, 16384(bts) Respond Fifo depth 2,4,8, 16, 32, Response(slave-to-master)FIFO 64,128,256 depth 512,10242048, 4096, 8192,16384 (bits) Master clock domain synchronizer depth 2, 3, 4, 5(bits) The number of pipeline stages in the clock crossing logic in the issuing master to target slave direction Increasing this value leads to a larger meantime between failures (MtBF You can determine the mtbf for a design by running a Time Quest timing alysi Slave clock domain synchronizer depth 2, 3, 4, 5(bits) The number of pipeline stages in the clock crossing logic in the target slave to master direction. Increasing this value leads to a larger meantime between failures(MTBF). You can determine the mtbf for a design b running a Time Quest timing analysis Avalon -MM Pipeline bridge The Avalon-MM Pipeline Bridge inserts a register stage in the Avalon- MM command and response paths It accepts commands on its Avalon- MM slave port and propagates the commands to its Avalon- MM master Qsys System Design Components era corporation Send Feedback 10-6 Q110 Avalon-MM Unaligned Burst Expansion Bridge 2014.06 port. The pipeline bridge provides separate parameters to turn on pipelining in the command and response networks You can use the Avalon-MM bridge to export a single avalon-MM slave interface to use to control multiple Avalon-MM slave devices. The pipelining feature is optional. You can optionally turn off the pipelining feature of this bridge igure 10-4: Avalon-MM Pipeline Bridge in a XAUI PHY Transceiver IP Core In this example, the bridge transfers commands received on its slave interface to its master port Exported to Embed Processor on PCe XAUI PHY PCS PMA Reconfiguraii LOW Latency Controller Controller Alt PMA Because the slave interface is exported to the pins of the device, having a single slave port, rather than separate ports for each slave device, reduces the pin count of the FPGA Avalon-MM Unaligned Burst Expansion Bridge The Avalon-MM Unaligned Burst Expansion Bridge aligns read burst transactions from masters connected to its slave interface, to the address space of slaves connected to its master interface. This alignment ensures that all read burst transactions are delivered to the slave as a single transaction Figure 10-5: Avalon -MM Unaligned Burst Expansion Bridge 64 bit Avalon MM Slave Slave Master Slave Master 32 bit Avalon-MM Unaligned Burst 64 bit Avalon -MM Slave Altera Corporation Qsys System Design Components Send feedback Q51025 2014.0630 Using the Avalon-MM Unaligned Burst Expansion Bridge 10-7 You can use the Avalon Unaligned Burst Expansion Bridge to align read burst transactions from masters that have narrower data widths than the target slaves. Using the bridge for this purpose improves bandwidth utilization for the master-slave pair, and ensures that un-aligned bursts are processed as single transactions rather than multiple transactions Note: Do not use the Avalon- MM Unaligned Burst Expansion bridge if any connected slave has read side effects from reading addresses that are exposed to any connected master's address map This bridge can cause read side effects due to alignment modification to read burst transaction addresses Note: For Qsys 14.0, the Avalon-MM Unaligned Burst Expansion Bridge does not support VHDL simulation Related Information Osys Interconnect Using the Avalon-MM Unaligned Burst Expansion bridge When a master sends a read burst transaction to a slave, the Avalon- MM Unaligned burst Expansion bridge initially determines whether the start address of the read burst transaction is aligned to the slave s memory address space. If the base address is aligned the bridge does not change the base address. If the base address is not aligned, the bridge aligns the base address to the nearest aligned address that is less than the requested base address The Avalon- MM Unaligned Burst Expansion Bridge then determines whether the final word requested b the master is the last word at the slave read burst address. If a single slave address contains multiple words ll of those words must be requested in order for a single read burst transaction to occur If the final word requested by the master is the last word at the slave read burst address, the bridge does not modify the burst length of the read burst command to the slave If the final word requested by the master is not the last word at the slave read burst address, the bridge increases the burst length of the read burst command to the slave The final word requested by the modified read burst command is then the last word at the slave read burst address The bridge stores information about each aligned read burst command that it sends to slaves connected to a master interface. When a read response is received on the master interface, the bridge determines if the base address or burst length of the issued read burst command was altered If the bridge alters either the base address or the burst length of the issued read burst command it receives response words that the master did not request. The bridge suppresses words that it receives from the aligned burst response that are not part of the original read burst command from the master Qsys System Design Components era corporation Send Feedback 10-8 Avalon- MM Unaligned Burst Expansion Bridge Parameters Q11025 2014.06.30 Avalon-MM Unaligned Burst Expansion Bridge Parameters Figure 10-6: Avalon-MM Unaligned Burst Expansion Bridge Parameter Editor A Avalon- MM Unaligned Burst Expansion Bridge-mm_unaligned_burst_expansion_ bridge_0 Avalon- MM Unaligned Burst Expansion bridge altera avalon mm unaligned burst expansion bridge Documentation Block Diagram T Parameters □ Show signals Data width 32 Address width(in WORDS) 29 unaligned_burst_expansion _bril Burstcount width 7 Maximum pending read transactions: 8 mo clock avalon Width of slave to optimize for 64 reset V Pipeline command signals avalon mm unaligned burst expansion bridge Cancel finish Table 10-2: Avalon-MM Unaligned Burst Expansion Bridge Parameters Parameter Description Data width Data width of the master connected to the bridge Address width(in WORDS) The address width of the master connected to the bridge Burstcount width The burstcount signal width of the master connected to the Driage Maximum pending read transactions The maximum pending read transactions interface property of the bridge Width of slave to optimize for The data width of the connected slave Supported values are 16,32,64,128,256,512,1024,2048,and4096bits. Note: If you connect multiple slaves, all slaves must have the same data width Altera Corporation Qsys System Design Components Send feedback Q51025 2014.0630 Avalon-MM Unaligned Burst Expansion Bridge Example 10-9 Parameter Description Ipeline command signals When turned on, the command path is pipelined, minimizing the bridge's critical path at the expense of increased logic usage and late Avalon-MM Unaligned burst Expansion bridge example Figure 10-7: Unaligned Burst Expansion Bridge The example below shows an unaligned read burst command from a master that the avalon-MM Unaligned Burst Expansion Bridge converts to an aligned request for a connected slave, and the suppression of words due to the aligned read burst command. In this example, a 32-bit master requests an 8-beat burst of 32-bit words from a 64-bit slave with a start address that is not 64-bit aligned Without Avalon-MM Unaligned Burst Expansion Bridge With Avalon-MM Unaligned Burst Expansion Bridge 0,1 X Transaction 1 0,1X*X 2, 3x TRansaction 2 1 X 2, 3XX 2X 4,5x Transaction 3 2X Bridge 4,5XX>Tr Alignment 3 X ↓6,7 x TRansaction4 3X 6,7XX 4 X 8,9X Transaction 5 4 X 8,9XX 5X Transaction 1 A B 5X Transaction 1 A B 6 X C D 6X C D 7 X EF 7X EF 8「X 8 Note: the bridge suppresses X* response words B C Because the target slave has a 64-bit data width, address l is unaligned in the slave's address space. As a result, several smaller burst transactions are needed to request the data associated with the master's read burst command With an Avalon- MM Unaligned Burst Expansion Bridge in place, the bridge issues a new read burst command to the target slave beginning at address 0 with burst length 10, which requests data up to the word stored at address 9 When the bridge receives the word corresponding to address 0, it suppresses it from the master, and then delivers the words corresponding to addresses I through 8 to the master. When the bridge receives the word corresponding to address 9, it suppresses that word from the master. Bridges Between Avalon and AXI Interfaces When designing a Qsys system, you can make connections between AXI and Avalon interfaces without the use of explicitly-instantiated bridges; the interconnect provides all necessary bridging logic. However, this does not prevent the use of explicit bridges to separate the axi and avalon domains Qsys System Design Components era corporation Send Feedback Q11025 10-10 AXI Bridge 2014.06.30 Figure 10-8: Avalon-MM Pipeline Bridge Between Avalon-MM and AXI Domains Using an explicit Avalon-MM bridge to separate the aXi and avalon domains reduces the amount of bridging logic in the interconnect at the expense of concurrency Shared avalon &axl domain Avalon-MM Network Ayalon-MM Avalon-MM Shared avalon aXl domains Avalon -MM Avalon -MM Pipeline Bridge Avalon -MM Avalon -MM AXI Bridge With an aXi bridge, you can influence the placement of resource-intensive components, such as the width and burst adapters. Depending on its use, an aXi bridge may reduce throughput and concurrency, in return for higher f Max d less log You can use an AXi bridge to group different parts of your Qsys system. Then, other parts of the system connect to the bridge interface instead of to multiple separate master or slave interfaces. You can also use an AXI bridge to export AXI interfaces from Qsys systems The example below shows a system with a single aXI master and three aXi slaves. It also has various interconnect components, such as routers, demuxes, and muxes two of the slaves have a narrower data width than the master; 16-bit slaves versus a 32-bit master. In this system, Qsys interconnect creates four width adapters and four burst adapters to access the two slaves. In this case, you could improve resource usage by adding an AXI bridge. This would result in Qsys having to add only two width adapters and two burst adapters, one pair for the read channels, and another pair for the write channel Altera Corporation Qsys System Design Components Send feedback
Avalon-ST single clock and dual clock fifo cores2011-07-13
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java jar包，亲测试可用 安全，可以对其进行数字签名，只让能够识别数字签名的用户使用里面的东西。 加快下载速度； 压缩，使文件变小，与ZIP压缩机制完全相同。 ...能够让JAR包里面的文件依赖于统一版本的类文件。...
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