altera标准SRDSDRAM控制器参考设计-verilog资源-CSDN文库

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pdf：1个

txt：1个

altera

SDRAM控制器

verilog

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Altera的Standard SDRAM控制器是为使用Verilog HDL进行FPGA设计的工程师们提供的一种高效、可配置的解决方案。这个参考设计旨在帮助用户在Altera FPGA中实现高性能的同步动态随机存取内存（SDRAM）接口。下面将详细介绍这个设计的关键知识点。 1. **同步动态随机存取内存 (SDRAM)**：SDRAM是一种广泛用于计算机系统中的内存类型，它能以与系统时钟同步的方式读写数据，提供较高的数据传输速率。在FPGA设计中，SDRAM常被用来存储大量的中间计算结果或实现高速缓存。 2. **Altera FPGA**：Altera是一家知名的FPGA制造商，其产品广泛应用在通信、汽车、工业、航空等多个领域。FPGA（Field-Programmable Gate Array）是一种可编程逻辑器件，允许用户根据需求自定义硬件逻辑。 3. **Verilog HDL**：Verilog是一种硬件描述语言，用于编写数字系统的规范，既可以描述行为，也可以描述结构。在本设计中，Verilog用于描述SDRAM控制器的逻辑功能和时序特性。 4. **SDRAM控制器**：SDRAM控制器是FPGA设计中不可或缺的部分，负责管理与SDRAM芯片的通信，包括初始化、时序控制、地址译码、数据传输等。Altera的Standard SDRAM控制器参考设计提供了完整的解决方案，包括所有必要的控制逻辑和接口。 5. **配置与可定制性**：此参考设计允许用户根据实际应用的需求进行配置，比如支持不同类型的SDRAM芯片、设置不同的数据宽度、时钟频率等。这大大简化了设计流程并提高了设计效率。 6. **仿真与验证**：文件列表中的`simulation`目录可能包含了用于验证设计正确性的仿真模型和测试向量。这些仿真工具可以帮助工程师在实际硬件实现之前发现潜在问题，确保设计的可靠性。 7. **源代码 (`source`目录)**：在这个目录中，用户可以找到用Verilog编写的SDRAM控制器源代码，包括模块定义、例化模板和相关逻辑。通过分析源代码，用户可以理解设计的内部工作原理并进行必要的修改。 8. **文档 (`doc`目录)**：`sdr_sdram.pdf`和`readme_sdr_sdram.txt`可能包含设计概述、使用指南、配置参数说明以及操作步骤等内容。这些文档对理解和使用该参考设计至关重要。 9. **实施与综合**：在理解并配置好参考设计后，工程师需要将其综合进FPGA的逻辑资源，并进行布局布线，最终生成适配特定Altera FPGA的比特流文件。通过深入学习和实践这个Altera Standard SDRAM控制器参考设计，开发者可以掌握在FPGA上实现高效SDRAM接口的技能，这对于构建高性能、实时处理的嵌入式系统具有重要意义。

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altera标准SRD SDRAM控制器参考设计-verilog.zip （11个子文件）

simulation

sdr_sdram_tb.v 22KB

sdr_sdram.pdf 896KB

readme_sdr_sdram.txt 372B

source

PLL1.v 5KB

sdr_data_path.v 3KB

Params.v 935B

Command.v 17KB

altclklock.v 8KB

sdr_sdram.v 7KB

control_interface.v 8KB

compile_all.v 206B

doc

White Paper

SDR SDRAM Controller

August 2002, ver. 1.1 1

M-WP-SDR-1.1

Introduction

The single data rate (SDR) synchronous dynamic random access memory (SDRAM) controller provides a simplified

interface to industry standard SDR SDRAM. The SDR SDRAM Controller is available in either Verilog HDL or

VHDL and is optimized for the Altera

APEX

™

architecture. The SDR SDRAM Controller supports the following

features:

■ Burst lengths of 1, 2, 4, or 8 data words

■ CAS latency of 2 or 3 clock cycles

■ 16-bit programmable refresh counter used for automatic refresh

■ 2-chip selects for SDRAM devices

■ Supports the NOP, READA, WRITEA, AUTO_REFRESH, PRECHARGE, ACTIVATE, BURST_STOP,

and LOAD_MR commands

■ Support for full-page mode operation

■ Data mask line for write operations

■ PLL to increase system performance

■ Support for data-path widths of 16, 32, and 64 bits

Figure 1 shows a system-level diagram of the SDR SDRAM Controller.

Figure 1. SDR SDRAM Controller System-Level Diagram

SDRAM Overview

SDRAM is high-speed dynamic random access memory (DRAM) with a synchronous interface. The synchronous

interface and fully-pipelined internal architecture of SDRAM allows extremely fast data rates if used efficiently.

Internally, SDRAM devices are organized in banks of memory, which are addressed by row and column. The number

of row- and column-address bits and the number of banks depends on the size of the memory.

SDR SDRAM

Controller

SDR SDRAM

CLK

CS_N

CKE

CAS_N

WE_N

DQM

RAS_N

CLK

CMD[1:0]

CMDACK

ADDR

DATAIN

DATAOUT

Altera Corporation SDR SDRAM Controller White Paper

SDRAM is controlled by bus commands that are formed using combinations of the RASN, CASN, and WEN signals.

For instance, on a clock cycle where all three signals are high, the associated command is a no operation (NOP). A

NOP is also indicated when the chip select is not asserted. Table 1 shows the standard SDRAM bus commands.

SDRAM banks must be opened before a range of addresses can be written to or read from. The row and bank to be

opened are registered coincident with the ACT command. When a bank is accessed for a read or a write it may be

necessary to close the bank and re-open it if the row to be accessed is different than the row that is currently opened.

Closing a bank is done with the PCH command.

The primary commands used to access SDRAM are RD and WR. When the WR command is issued, the initial col-

umn address and data word is registered. When a RD command is issued, the initial address is registered. The initial

data appears on the data bus 1 to 3 clock cycles later. This is known as CAS latency and is due to the time required to

physically read the internal DRAM core and register the data on the bus. The CAS latency depends on the speed of

the SDRAM and the frequency of the memory clock. In general, the faster the clock, the more cycles of CAS latency

are required. After the initial RD or WR command, sequential read and writes continue until the burst length is

reached or a BT command is issued. SDRAM memory devices support burst lengths of 1, 2, 4, or 8 data cycles. The

ARF is issued periodically to ensure data retention. This function is performed by the SDR SDRAM Controller and is

transparent to the user.

The LMR is used to configure the SDRAM mode register. which stores the CAS latency, burst length, burst type, and

write burst mode. Consult the SDRAM specification for additional details.

SDRAM comes in dual in-line memory modules (DIMMs), small-outline DIMMs (SO-DIMMs) and chips. To reduce

pin count SDRAM row and column addresses are multiplexed on the same pins. SDRAM often includes more than

one bank of memory internally and DIMMS may require multiple chip selects.

Table 1. SDRAM Bus Commands

Command Abbreviation RASN CASN WEN

No operation NOP H H H

Active ACT L H H

Read RD H L H

Write WR H L L

Burst terminate BT H H L

Precharge PCH L H L

Autorefresh ARF L L H

Load mode register LMR L L L

Altera Corporation SDR SDRAM Controller White Paper

Functional Description

Table 2 shows the SDR SDRAM Controller interface signals. All signals are synchronous to the system clock and

outputs are registered at the SDR SDRAM Controller’s outputs.

Table 2. Interface Signals

Signal Name Active I/O Description

CLK Clock NA Input System clock.

RESET_N Reset Low Input System reset.

ADDR[ASIZE-1:0] Memory address NA Input Memory address for read/write requests. Width is set by

ASIZE.

CMD[2:0] Command NA Input Command request.

CMDACK Command acknowledge High Output Acknowledgment of the requested command.

DATAIN[DSIZE-1:0] Input data NA Input Input data bus. Width is set by DSIZE.

DATAOUT[DSIZE-1:0] Output data NA Output Output data bus. Width is set by DSIZE.

DM[(DSIZE/8)-1:0] Data mask High Input Masks individual bytes during data write

SA[11:0] Address bus NA Output SA[11:0] are sampled during the ACT command to latch

the row address. SA[n:0] are sampled during the RD/WR

command to latch the column address where n depends on

the size of SDRAM used. SA[10] is sampled during the

PCH command to determine if all banks are to be pre-

charged or the bank selected by BA[1:0]. The address out-

puts also provide the op-code during the LMR command.

BA[1:0] Bank address NA Output These signals determine to which bank the ACT, RD, WR, or

PCH command is applied.

CS_N[1:0] Chip selects Low Output SDRAM chip selects.

CKE Clock enable High Output SDRAM CKE input.

RAS_N Row address strobe Low Output SDRAM command input.

CAS_N Column address strobe Low Output SDRAM command input.

WE_N Write enable Low Output SDRAM command input.

DQ[DSIZE-1:0] Data bus NA I/O SDRAM data bus.

DQM[(DSIZE/8)-1:0] Data mask High Output SDRAM data masks, mask individual bytes during data

write.

Altera Corporation SDR SDRAM Controller White Paper

SDRAM Controller Command Interface

The SDR SDRAM Controller provides a synchronous command interface to the SDRAM and several control regis-

ters. Table 3 shows the commands, which are described in following sections. The following rules apply to the com-

mands:

■ All commands, except NOP, are driven by the user onto CMD[2:0]; ADDR and DATAIN are set appropri-

ately for the requested command. The controller registers the command on the next rising clock edge

■ To acknowledge the command the controller asserts CMDACK for one clock period

■ For READA or WRITEA commands, the user should start receiving or writing data on DATAOUT and

DATAIN

■ The user must drive NOP onto CMD[2:0]by the next rising clock edge after CMDACK is asserted

NOP Command

NOP is a no operation command to the controller. When NOP is detected by the controller, it performs a NOP in the

following clock cycle. A NOP must be issued the following clock cycle after the controller has acknowledged a com-

mand. The NOP command has no affect on SDRAM accesses that are already in progress.

READA Command

The READA command instructs the SDR SDRAM Controller to perform a burst read with auto-precharge to the

SDRAM at the memory address specified by ADDR. The SDR SDRAM Controller issues an ACTIVATE command

to the SDRAM followed by a READA command. The read burst data first appears on DATAOUT (RCD + CL + 2)

after the SDR SDRAM Controller asserts CMDACK. During a READA command the user must keep DM low. When

the controller is configured for full-page mode, the READA command becomes READ (READ without auto-pre-

charge). Figure 2 shows an example timing diagram for a READA command. The following sequence describes the

general operation of the READA command:

■ The user asserts READA, ADDR and DM

■ The SDR SDRAM Controller asserts CMDACK to acknowledge the command and simultaneously starts issu-

ing commands to the SDRAM devices

■ One clock after CMDACK is asserted, the user must assert NOP

■ The CMDACK presents the first read burst value on DATAOUT, the remainder of the read bursts follow every

clock cycle

Table 3. Interface Commands

Command Value Description

NOP 000b No operation.

READA 001b SDRAM read with auto precharge.

WRITEA 010b SDRAM write with auto precharge.

REFRESH 011b SDRAM auto refresh.

PRECHARGE 100b SDRAM precharge all banks.

LOAD_MODE 101b SDRAM load mode register.

LOAD_REG1 110b Load controller configuration register.

LOAD_REG2 111b Load controller refresh period register.

Altera Corporation SDR SDRAM Controller White Paper

Figure 2. READA Timing Diagram

WRITEA Command

The WRITEA command instructs the SDR SDRAM Controller to perform a burst write with auto-precharge to the

SDRAM at the memory address specified by ADDR. The SDR SDRAM Controller will issue an ACTIVATE com-

mand to the SDRAM followed by a WRITEA command. The first data value in the burst sequence must be presented

with the WRITEA and ADDR address. The host must start clocking data along with the desired DM values into the

SDR SDRAM Controller (t

RCD

– 2) clocks after the SDR SDRAM Controller has acknowledged the WRITEA com-

mand. See a SDRAM data sheet for how to use the data mask lines DM/DQM.

When the SDR SDRAM Controller is in the full-page mode WRITEA becomes WRITE (write without auto-pre-

charge). Figure 3 shows an example timing diagram for a WRITEA command. The following sequence describes the

general operation of a WRITEA command:

■ The user asserts WRITEA, ADDR, the first write data value on DATAIN, and the desired data mask value on

■ The SDR SDRAM Controller asserts CMDACK to acknowledge the command and simultaneously starts issu-

ing commands to the SDRAM devices

■ One clock after CMDACK was asserted, the user asserts NOP on CMD

■ The user clocks data and data mask values into the SDR SDRAM Controller through DATAIN and DM

Address

1234...n-6n-5n-4

Row

Column

CLK

CMD

CMDACK

ADDR

DATAOUT

DQM

RAS_N

CAS_N

WE_N

CS_N

CKE

NOP

READA

1 2 ... n-8 n-7 n-6 n-5 n-4

NOP

D.C.

D.C. = Don't Care

D.C.

PRECHARGE NOP

nn-1n-2n-3

n-1n-2n-3

评论收藏

内容反馈

WESTMULAN

2015-06-08

官方的SDRAM控制器，但不好移植到Xilinx上
starmoon9527

2014-07-10

研究中，不够完整
sophy212

2013-10-09

东西不全，代码还看不了不知道为什么
叫什么好呢80

2013-12-02

正在研究，应该还是不错的
mixwill8

2014-01-16

非常好用，不过有些地方要稍微修改修改

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