USER'S MANUAL
S3C2416
16/32-Bit RISC Microprocessor
October 2008
REV 1.10
Confidential Proprietary of Samsung Electronics Co., Ltd
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S3C2416 16/32-Bit RISC Microprocessor
User's Manual, Revision 1.10
Publication Number: 21.10-S3-C2416- 082008
Copyright © 2008 Samsung Electronics Co.,Ltd.
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NOTIFICATION OF REVISIONS
ORIGINATOR: Samsung Electronics, LSI Development Group, Gi-Heung, South Korea
PRODUCT NAME: S3C2416 RISC Microprocessor
DOCUMENT NAME: S3C2416 User's Manual, Revision 1.10
DOCUMENT NUMBER: 21.10-S3-C2416-082008
EFFECTIVE DATE: October, 2008
DIRECTIONS: Revision 1.10
REVISION HISTORY
Revision No Description of Change Refer to Author(s) Date
1.00 Initial release - AP app part. August 27, 2008
1.10 Overview, System controller, DMA controller,
I/O ports, LCD controller are updated.
- AP app part. October 06, 2008
REVISION DESCRIPTIONS FOR REVISION 1.10
Chapter
Chapter Name Page
Subjects (Major changes comparing with last version)
1. Overview 1-2
Way number of Cache Memory is corrected.
2. System controller 2-1,6,8,9
Camera related explanation is removed.
8. DMA controller 8-2
DMA request sources are corrected.
8. DMA controller 8-16,17
Referred Register name, bit and pages are corrected.
10. I/O ports 10-37
CF related description is removed.
21. LCD controller 21-23
Camera related explanation is removed.
S3C2416X RISC MICROPROCESSOR i
Table of Contents
Chapter 1 Product Overview
1 Introduction ...............................................................................................................................................1-1
2 Features....................................................................................................................................................1-2
3 Block Diagram...........................................................................................................................................1-5
4 Pin Assignments .......................................................................................................................................1-6
4.1 Signal Descriptions..........................................................................................................................1-24
4.2 S3C2416 Operation Mode Description ...........................................................................................1-31
4.3 S3C2416 Memory MAP and Base Address of Special Registers...................................................1-32
Chapter 2 System Controller
1 Overview ...................................................................................................................................................2-1
2 Feature......................................................................................................................................................2-1
3 Block Diagram...........................................................................................................................................2-2
4 Functional Descriptions.............................................................................................................................2-3
4.1 Reset Management and Types .......................................................................................................2-3
4.2 Hardware Reset...............................................................................................................................2-3
4.3 Watchdog Reset..............................................................................................................................2-4
4.4 Software Reset ................................................................................................................................2-5
4.5 Wakeup Reset.................................................................................................................................2-5
5 Clock Management...................................................................................................................................2-6
5.1 Clock Generation Overview.............................................................................................................2-6
5.2 Clock Source Selection ...................................................................................................................2-6
5.3 PLL (Phase-Locked-Loop) .............................................................................................................. 2-8
5.4 Change PLL Settings In Normal Operation.....................................................................................2-8
5.5 System Clock Control......................................................................................................................2-9
5.6 ARM & BUS Clock Divide Ratio ......................................................................................................2-10
5.7 Examples for configuring clock regiter to produce specific frequency of AMBA clocks..................2-11
5.8 ESYSCLK Control ...........................................................................................................................2-12
6 Power Management..................................................................................................................................2-13
6.1 Power Mode State Diagram ............................................................................................................2-13
6.2 Power Saving Modes.......................................................................................................................2-14
6.3 Wake-Up Event
...............................................................................................................................2-19
6.4 Output Port State and STOP and SLEEP Mode .............................................................................2-19
6.5 Power Saving Mode Entering/Exiting Condition..............................................................................2-20
7 Register Descriptions................................................................................................................................2-21
7.1 Address Map ...................................................................................................................................2-21
