AR9341.pdf

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高通qualcomm 802.11n 2x2 2.4GHz WLAN SOC 数据手册说明书 高通qualcomm 802.11n 2x2 2.4GHz WLAN SOC 数据手册说明书
ATHEROS Data Sheet October 2012 AR9341 Highly-Integrated and Feature-Rich IEEE 802.11n 2x2 2.4 GHz Premium soc for Advanced wlan platforms General Description Features The Atheros ar9341 is a highly integrated and 74Kc MIPS processor with 64 KB I-C che and feature-rich ILLL 802.11n 2x2 2.4 GIIz System 32 KB D-Cache, operating at up to 535 MIz on-a-Chip(Soc)for advanced WlAN platforms a External 16-biL DDRI, DDR2 op rating al up It includes a mips 74Kc processor, five port ILll tu 225 MHz(450 M transfe s/sec) 802.3 Fast Ethernet Switch with MAC/PHY, one ■ SPINOR到 ash memory upport USB 2.0 MAC/PHY, and external memory 10/100 Ethernet Switch w h five IEEE 802.3 interface for serial Flash, dDR1 or DDR2, I-S/ Ethernet Lan ports SPDIF-Out audio interface, SLIC VOIP/PCM 802.3az Energy Efficient Ethernet compliant interface. two UARts, and gPios that can be Hardware-based nat aCl accelerators for used for LED controls or other general purpose Ethernet inte face interface configurations One uSB 2.0 controller with built-in MAC/ The AR9341 supports 802.1In operations up to PHY supports Host or Device mode Boot from external CPU via USB, eliminating 144 Mbps for 20 MHz and 300 Mbps for 40 MHz ne d for external flash and 802.11b/g data rates. Additional features include maximal Likelihood (ml) decoding I2S/SPDIF-out audio interface Low-Density Parity Check (LDPC), Maximal LIC for VOIP/PCM Ratio Combining (Mrc), Tx Beamforming One low-speed UART(115 Kbps), one high CIXBF), and On-Chip One-fime Programmable speed UART( Mbps), and multiple GPio (OTP) memory pins for general purpose I/O Fully integrated RF Front-End including PAs The AR9341 supports booting from NOR Flash. dinas When connecting the ar9341 to an external host Optional external LNA/PA through the usB Device interface, th AR9341 25 MHZ or 40 MHz reference clock input can offload the host CPU from computation- 1.2 V switching regulator intensive functions, allowing it to f cus on its advanced power management with dynamic dedicated tasks clock switching for ultra-low powcr modes 150-pin dual-row LPCC package AR9341 System Block Diagram 2.4 GHz Serial flash and CDR Interface DDR1/DDR2 5x Fast Ethernet RF 802.11n Controller and AN/WAN Ports Ethernet interface Front WLAN NOR Flash MAC/BB/ Radio Memory Interface Speed uart k UARt Interface Low Speed JAFT UART Interfac色 ckC USB MAC/PHY →UsB2.0 Interface Processor External interface 卡GPI0s/LEDs IS/SPDIF Audio interrace Hardware WOIP/P AR9341 Accelerators 25 or 40 MHz Crystal 02011-2012by Athercs Communications, Inc. All rights reserved. AtherosB, Atheros Driven, Align, Atheros xxo, Driving the wireless Futured, IntellDro, ETHgS), QUER Total 802.11e, U-Narw, wake on wireless, wireless Fulture. Unleashed Nowa, and xspanop, are regis ered by Abens communications, nc. Atheros ssim, sgmal-sustain Smarten Lag y, ar TM are trademarks of Atheros Communications, Inc. The Atheros logc is a registered trademark of Atheros Communications, Inc. All other trademarks are the proper ty of their respective holders. Subjec: to change without noti COMPANY CONFIDENTIAL Table of Contents 1 Pin Descriptions 21 2.14Usb2.0Interfacewww...51 2 Functional Description………29 3 Ethernet Subsystem……………53 2.1 Functional Block Diagram……… 29 3.1 GMACO and gmac1 3.1.3 Ingress and egress flow ofd ta a d 2.2 Bootstrap optior Control information 2.3 RESET 32 32 GMAC Descriptor Structure:Rx…….56 2.4 PLL and Clock control ........................33 3.2.1 Start Address for packet data 2.4.1 Full Chip Clocking Structure. 33 ( PKT START ADDR)…….56 2.4.1 CPU PLL… 34 3.2.2 Packet Size and Flags(PKT_size) 2.42 DDR PLI .34 24.3 Audio pll∴…..….35 3.2.3 Next Descrip or Address 2.5 MIPS Processor……….35 ( NEXT DESCRIPTOR)… 2.5.1 Configuration 35 3.3 GMAC Descriptor Structure: Ix...57 2.6 AddreSs mae∴ 33 1 Start Address for Packet Data PKT_START_ADDR) 2.7 DDR Memory controller 36 3.3.2 Packet Size and Flags(PKT_siZE 2.7. 1 DDR Configurations...... 36 58 27.2 DDR1 and ddr2 Initialization 3.3.3 Next Descriptor Address Sequences…………37 ( NEXT DESCRIPTOR)… 273 Address Mapping…… 3.4 NAT LUT Structure: Ingress and Egress 2.7.4 Refresh 40 59 2. 8 SLIC 3.5 Hardware Ager: Ingress and Egress ...60 2.8.1 Overview… 41 3.6 Setup and Data/Packet Flow 2.8.2 SLIC Interface …41 3.6.1 Ingress∴ 60 28.3 Transmit∴ 3.6.2 Egress…………61 2.8.4 Receive .41 3.7 ACL 28.5 SLIC Interf e Signals………42 3.7.1 ACL Data structure 2.8.6 SLIC Mast r and Slave Modes. 42 3.7.2 Global rules 2.9 Segmentatio Desegmentation/ 3.7.3 Entry programming Checksum accelerator 43 3.7.4 ACL Programming and Software 2.10 GPIO Fle 210.1 GPIO Output………....46 3.8 Ethernet Switch 2.02 GPIO Input…………………48 3.9 Five-Port ethernet switch 67 2 11 Serial Flash SPI/ROM 49 3.91 Overview∴ 211.1 SPI Operations………… 3.92 Basic Switch Operation……68 2.11.2 Write Enable ,................................49 3.9.3 Media Access Controllers (mac) 2.11.3 Page program 49 2. 11. 4 Page re 49 3.9.4 ACL 212 High-Speed UART Interface…………50 3.9.5 Register Access 2.12.1 Transmit(Tx)……………50 3.9.6 LED Control 2.12.2R 50 3.9.7 VLANs 213 Low-Speed UART Interface……150 3.9.8 ieee Port Security……………0 Atheros Communications, Inc AR9341 Highly-Integrated and Feature-Rich 802. 11n 2X2 2.4 GHz Soc 1 3.9.9 Mirroring 6.3 802.11b/ g Legacy Mode 104 3.9.10 Broadcast/Multicast/Unknown 6.3.1 Transmitter 104 Unicast ..........................................70 6.3.2 Receiver 3.9.11 IGMP/MLD Snooping ...70 3.912 Spanning Tree……… 71 7 Radio block∴105 3.9.13 MIB /Statistics Counters .71 7.1 Receiver (rx) block .......................106 3. 9.14 Atheros Header Configuration. 73 7.2 Transmitter(Tx) Block……107 3.9. 15 IEEE 802. 3 Reserved group 7.3 Synthesizer(SYNTH) Block ,108 Addresses Filtering Control……73 7. 4 Bias /Control(Bias) Block 108 3.9.16 PPPoE Header Removal 74 3.10 Ethernet Core Reset..........75 8 Register Descriptions……,109 8.1.1 DDR DRAM Contiguration..110 8.1 DDR Registe 4 Audio interface…77 4.1 Overview DDR CONFIG)… 4.2 Audio pll 8.1.2 DDR DRAM Configuration 2 4.3 I2S Interface 78 ( DDR CONFIG2)………111 4.3.1 External dac 78 8.1.3 DDR Mode value 4.3.2 Sample Sizes and rates DDR MODE REGISTER)……111 81.4 DDR Extended mode 4.3.3 Stereo Software Interface ...........78 (DDR_EXTENDED_ MODE_ REGIS 4.4 SPDIF INTERFACE 1垂非;音着垂看音垂非垂 78 TER) 112 4.5 Mailbox( DMA Controller)…………9 8.1.5 DDR Control(DDR_ CONtrol) 4.5.1 Mailboxes……9 112 4.52 MBOX DMA Operation………79 8.1.6 DDR Refresh Control and 4.5.3 Software flow Control .... 80 Configuration(DDR_ REFresh) 4.5.4 Mailbox Error Conditions..80 112 4.5.5 MBOX-Specific Interrupts 8.1.7 DDR Read Data Capture Bit Mask DDR RD DATA THIS_ CYCLE) 5 WLAN Medium access control 112 (MAC81 8.1.8 DQS Delay Tap Control for Byte O (TAP_CONTROL-O 113 5.1 Overview ,81 8.1.9 DQS Delay Tap Control for Byte 1 5.2 Descriptor .81 (TAP CONTROL__ 113 53 Descriptor Format……….82 8.1.10 DQS Delay Tap Control for Byte 2 54 Queue C ntrol Unit(QCU)…… 100 ( TAP CONTROL_2)…….113 5.5 DCF Con rol Unit(dCu) 8.1.11 DQS Delay Tap Control for Byte 3 ( AP CONTROL_3)…114 5.5. DCU State Information 8.1.12 GMACO Interface Write Buffer 5.6 Protocol control unit(PCU)……….101 Flu 5.7 Register Programming Details for (DDR- WB FLUSH_ GMACO) 114 Observing WMAC Interrupts 102 8. 1.13 GMAC1 Interface Write Buffer Flush 6 Digital PhY Block......103 DDR_WB_FLUSH_GMAC1. 114 6.1 Overview 103 8. 1.14 USB Interface Write Buffer flush 62802.11n( MIMO) Mode…… DDWB_ FLUSH USB)∴……114 621 Transmitter(①x)… 103 8.1.15 WMAC Interface Write Buffer flush 6.2.2 Receiver(Rx) 104 DDR WB FLUSH_ WMAC). 115 8.1.16 SRC1 Interface Write Buffer flush 2 AR9341 Highly-Integrated and Feature-Rich 802.11n 2X2 2.4 GHz Soc Atheros Communications, Inc. October 2012 COMPANY CONFIDENTIAL DDR WB FLUSH SRO1)…115 SUSPEND_RESUMECNTR)126 8. 1.17 SRC2 Interface Write Buffer flush 8.4 GPIO Registers ① DDR WB_ FLUSH SRO2)…115 8.4.1 GPIO Output Enable(GPIO_Oe) 8.1.18 DDR2 Configuration 128 (DDR_DDR2_CONFIG) 8.4.2 GPIO Input Value(GPIO_IN) 128 81.19 DDR EMR2( DDR EMR2)……116 8.4.3 GPIO Output Value(GPIO Out 8.1.20 DDR EMR3 (DDR_EMR3)……116 8.1.21 DDR Bank arbiter Per Client burst 8.4.4 GPIO Per Bit Set(GPIO SET). 128 Size( DDR BURST)…117 8.4.5 GPIO Per Bit Clear(GPIO_CLEAR) 8.1.22 DDR Bank arbiter Per client burst 129 size2( DDR BURST2)…… 117 8.4.6 GPIO Interrupt Enable(GPIO_INt) 8. 1.23 AHB Master Timeout Control 129 (AHB_ MASTER TIMEOUT_ MAX 8.4.7 GPIO Inter upt Type 117 (GPIO INT-TYPE 129 8. 1.24 AHB Timeout Current Count (AHB MASTER TIMEOUT_ CUR 8.4.8 GPIO I terrupt Polarity (GPIO_ INT POLARITY)………129 ……18 84.9 GPIO Interrupt Pending 8.1.25 Timeout slave address (GPIo_ INT PENDING)…….130 (AHB_ MASTER- TIMEOUT_SLV ADDR)……118 8.4.10 GPIO Interrupt Mask (GPIO_INT_MASK) 130 8. 1.26 DDR Controller Configuration 8.4.11 GPIO Ethernet led Routing select ① DDR CTL_ CONFIG)………118 (GPIO_IN_ETH_ SWITCH_LED) 8. 1.27 DDR Self refresh Control (DDR_SF_CTL) 119 8.4.12 GPIO Function o 8.1.28 Self Refresh Timer (sF_TIMEr) 19 (GPIO- OUT_ FUNCTIONO).131 8. 1. 29 WMAC Flush(WMAC FLUSH) 8.4.13 GPIO Function 1 119 (GPIO- OUT_- FUNCTION1).131 8.2 UARTO (LOW-Speed) Reg ste s .....120 8.4.14 GPIO Function 2 8.2.1 Receive Buffer(rbr).....120 (GPIO_ OUT_ FUNCTION2).132 82.2 Transmit Holdi g(THR)……120 8.4.15 GPIO Function 3 823 Divisor la ch low(DLL)……121 (GPIO OUT FUNCTION3).132 8.2.4 Divisor Latch High (DLH)..12 8.4.16 GPIO Function 4 82 Inte rupt Enable(IER)……121 (GPIO__OUT_FUNCTION4).132 8.2.6 I terrupt Identity (IIr) 122 8.4. 17 GPIO In Signals O 82.7 FIFO Control(FCR)………122 (GPIO_ IN ENABLEO)… 133 828 Line control(LCR)……123 8.4.18 GPIO In Signals 1 GPIO_IN_ENABLE1) 133 82.9 Modem Control (MCr) 123 8.4.19 GPIO In Signals 4 8.2.10 Line status(LSR)…… 124 (GPIO_ IN ENABLE4)………133 8211 Modem status(MSR)…….124 8.4.20 GPIO In Signals 9 8.3 USB Registers 125 GPIO_ IN_ENABLE9) 34 8.3.1 USB Power Control 8. 4.21 GPIO Function (USB_ PWRCTL)………125 (GPIO_ FUNCTION)………134 8.3.2 USB Configuration Control 8.5 PLL Control registers 135 (USB_CONFIG 125 8.5.1 CPU Phase Lock Loop 8.3.3 USB Device Suspend control Configuration (USB_DEV_SUSPEND_CTRL) 126 (CPU_ PLL CONFIG)… 136 8.3.4 USB Suspend resume Counters Atheros Communications, Inc AR9341 Highly-Integrated and Feature-Rich 802. 11n 2X2 2.4 GHz Soc 8.5.2 DDR PLL Configuration (RST__WMAC_INTERRUPT_ STAT (DDR_PLL_CONFIG) 136 147 8.5.3 CPU DDR Clock Control 8.6.11 Reset bootstrap (CPU_DDR_CLOCK-CONTROL (KS_ BOOTSTRAP)…… ,148 137 8.6.12 Sticky Register Value 8.5.4 Switch Clock Source Contro ( SPARE SIKY_REG[O:0])……148 SWITCH_ CLOCK_CONTROL) 8.7 GMAC Interface Registers 138 8.7.1 Ethernet Configuration 8.5.5 Current Dither Logic Output ETH CFO)…… 14 (CURRENT_PLL_ DITHER). 138 8.7.2 LUTs Ager Interrupt st tus 8.5.6 AudiO PLL Configuration (LUTS_ AGER_INT) 149 (AUDIO_PLL _CONFIG) 139 8.7.3 LUTs Ager Interrupt mask 8.5.7 Audio Pll modulation Control (LUTS_ AGER INTR_MASK). 150 (AUDIO PLL MODULATION 139 8.7.4 GMACO RX Data CRC Calculation Control 8.5.8 Audio Pll Jitter Control (GMACO- RXDATA_ CRC- CONTR (AUDIO PLL MOD STEP).... 140 OL …150 8.5.9 Current Audio Modulation Output 8.7.5 GMACO Valid rX Data CRC Value (CURRENT_ AUDIO PLL MODU (GMACO_ RXDATA_ CRC)..150 LATION 8.5.10 DDR PLL Dither parameter 8.8 GMACO Ingress NAT /Egress NAT (DDR_PLL_DITHER) Registers 151 8.5.11 CPU PLL Dither parameter 8.8.1 Egress CPU Requested LUT Entry (CPU PLL DITHER 141 Lookup(EG_CPU_REQ)……154 8.8.2 Egress CPU Request Status 8.6 Reset registers............142 王G_ CPU_REQ STATUS)……154 8.6.1 General Purpose Timers 8.8.3 Egress dwo Information (RST_ GENERAL_TIMERX).1 2 EG INFO DWO 155 8.6.2 General Purpose fime sr load 8.8.4 Egress CPU Related Dwo (RST- GENERAL_ TIMER_ RELOA Information DX) …4143 (EG_ CPU REQUESTED INFO_D 8.6.3 Watchdog Time Co trol WO)…. .15 (RST_WATCHDOG_TIMER_CON 8.8.5 Egress Dwo Key (EG KEY DwO IROL)….….……143 155 8.6.4 Watchdog timer 8.8.6 Egress DW1 Key(EG__DW1) (RST_ WATCHDOG_TIMER). 143 8.6.5 Mi cellaneous Interrupt status 8.8.7 Egress Ageout DWO Key (RST_ MISC_INTERRUPT_STATUS (EG_AG酿 R_KEY_DW0)………155 ).1441 8.8.8 Egress Ageout DW1 Key 866 Miscellaneous interrupt mask (EG_AGER_KEY_DW1) (RST_MISC_INTERRUPT_MASK) 145 8.8.9 Egress Ager FIFO Signals (EG_ AGER INFC)…………,156 8.6. 7 Global Interrupt status (RST_GLOBAL_INTERRUPT_STA 88.10上 gress Memory( EG MEM)…156 TUS …145 8.8.11 Egress Memory DwO 868 Reset( RST RESET)………146 EG_MEM_DWU)3…………………156 8.6.9 Chip Revision ID 8.8. 12 Egress Memory DW1 (RST_REVISION_ID) ( EG MEM_DW1)…… 157 8.6.10 WMAC Interrupt status 8.8. 13 Egress Memory dW2 EG MEM DW2)… 157 4. AR9341 Highly-Integrated and Feature-Rich 802. 11n 2X2 2. 4 GHz Soc Atheros Communications, Inc. October 2012 COMPANY CONFIDENTIAL 8.8. 14 Egress Link List(EG_ LINKLIST) 8.8.35 Ingress Memory DW3 157 IG MEM DW3)…… ..162 8.8.15 Egress Sub-Table Data 8.8. 36 Ingress Link List(IG_LINKLIST 上G_ SUBTABLE)…… 157 163 8.8.16 Egress Timer Ager values 8.8. 37 Ingress sub-Table data (EG_AGER_TCK)……158 ( G SUBTABLE)…… 8.8.17 Egress Ager Timeout 8.8.38 Ingress Timer Ager Values (EG_AGER_TIMEOUT) .158 (G_ AGER TICK)…………163 8.8.18 Ingress CPU Requested LUT Entry 8.8.39 Ingress Ager Timeout Lookup(IG_ CPU_ REQ)…….158 (G_AGER- TIMEOUT) 8. 8.19 Ingress CPU Request status 8.8.40 Tx QoS Arbiter C figuration (IG_ CPU_ REQ STATUS)……159 ( TXQOS_ARB_CFG)…………164 8.8.20 Ingress DWO Information 8.8. 41 x Status nd packet Count (IG_ INFO DW0)………….159 ( DMATXSTATUS)…………,164 8.8.21 Ingress Dw1 Information 8.8.42 Local mac Address dwordo (IG_INFO__DW1 ( LCL MAC ADDR DW0)……164 8.8.22 Ingress dW2 Information 88.43 Lo al mac address dword 1 (G INFO DW2) ( CL MAC ADDR DW1)……165 8.8.23 Ingress DW3 Information 8.8.44 Next Hop Routers Mac address (G_INFO_DW3 Dword 8.8.24 Ingress CPU Related Dwo (NXT_HOP_DST_ADDR_DWO Information 165 IG_CPU_REQUESTED_INFO_DW 8.8.45 Next Hop Routers MAc Address 0 160 Dword 8.8.25 Ingress CPU Related dw1 (NXT_HOP_DST_ADDR_DW1 Information 165 (G_CPU_REQUESTED INFO_DW 8.8.46 Local Global IP Address o 1) 160 (GLOBAL-IP_ADDRO) 8.8.26 Ingress CPU Related DW2 8.8.47 Local global ip Address 1 Information ( GLOBAL IP ADDR1)…………165 (G_CPU_REQUESTED_INFO_DW 8.8.48 Local Global ip Address 2 (GLOBAL_IP_ ADDR2)...166 8.8.27 Ingres CPU Related DW3 8.8.49 Local Global ip Address 3 Information ( GLOBAL IP ADDR3)… 166 (G_CPU_REQUESTED_INFO_DW 8.8. 50 Egress NAT Control and Status 161 (EG NAT CSR) 88.28 Ingress Dwo Key(Ig Key dwo 8.8.51 Egress NaT Counter 161 ( EG NAT CNTR)………167 88.29 Ingress Ageout DWO Key 8.8.52 Ingress nat Control and status ( G AGER K上YDW)3…….161 ( IG NAT CSR)… 167 8.8.30 Ingress Ager FIFo Signals 8.8.53 Ingress nat Counter (IG_AGER_INFO) (G_NAT_CNTR 8.8.31 Ingress Memory (IG MEM).162 8.8.54 Egress ACL Control and Status 8.8.32 Ingress Memory dwo EG_ACL_CSR)…… GMEM_DW0)……….162 8.8.55 Ingress acl control and status 8.8.33 Ingress Memory dw1 G_ACL_CSR)…… (G_MEM_DW1) 162 8.8.56 Egress ACL. CMDO and Action 8.8.34 Ingress Memory DW2 (EG_ACL_CMDO_AND_ACTION) ( IG MEM_DW2)…… 162 Atheros Communications, Inc AR9341 Highly-Integrated and Feature-Rich 802. 11n 2X2 2.4 GHz Soc 169 8.8.80 Ingress ACL Counter Group 14 8.8.57 Egress ACL CMDI, CMD2, CMD3 IG ACL COUNTER GRP14)176 CMDA (EG_ACL_-CMD1234).169 8.8.81 Ingress ACL Counter Group 15 8.8.58 Egress ACL OPERANDO (G_ACL_COUNTER_-GRP15)176 ( EG ACL_ OPERAND0)…….169 8.8.82 Egress ACL Counter Group o 8.8.59 Egress ACL OPERANDI (EG_ACL_COUNTER_GRPO)177 ( EG ACT, OPERAND1)………170 8.8.83 Egress ACL Counter group 1 8.8.60 Egress aCl Memory Control (EG_ ACL_COUNTER_GRP1)177 (EG_ACL_MEM_CONTROL). 170 8.8.84 Egress ACL Counter Group 8.8.61 Ingress a cl cmdo and action (EG_ACL_COUNTER_ GRP2) 177 (G_ACL_CMDO_AND_ACTION) 8.8.85 Egress ACL Counter Group 3 171 EG_ACL_COUNTER_GRP3)177 8.8.62 Ingress ACL CMDl, CMD2, CMD3, 8.8.86 Egress ACl C un er Group 4 CMDA (IG_ACL__CMD1234).171 8. 8.87 Egress ACL Counter Group s o (EG_ ACL_COUNTER_-GRP4)12 8.8.63 IngreSs ACL oPerando (G_ ACL_ OPERANDO 171 EG_ACL COUNTER_GRP5)178 8.8.64 Egress ACL OPEraND1 8.8.88 Egress ACL Counter Group 6 EG ACL OPERAND1)……172 EG ACL COUNTER GRP6) 178 8.8.65 Ingress ACL Memory Control 8.8.89 Egress ACL Counter Group 7 (G_ACL_MEM_CONTROL). 172 (EG_ACL_COUNTER_GRP7 178 8.8.66 Ingress ACl Counter Group o 8.890 Egress ACL Counter Group 8 (G_ACL_COUNTER_-GRPO) 173 (EG ACL COUNTER GRP8)179 8.8.67 Ingress ACL Counter Group 1 8. 8.91 Egress ACl Counter grour (G_ACL_COUNTER_GRP1).173 (EG_ACL_COUNTER_GRP9)179 8.8.68 Ingress ACL Counter group 2 8.8.92 Egress ACL Counter group 10 (IG_ACL_COUNTER_GRP2) 173 (EG ACL COUNTER GRP10)179 8.8.69 Ingress acl Counter group 3 8.8.93 Egress ACL Counter Group 11 (G_ACL_COUNTER_GRP3).173 (EG_ACL_COUNTER_GRP11)179 8.8.70 Ingress ACL Counter group 4 8.8.94 Egress ACL Counter Group 12 (G_ACL_COUNTER_GRP4)174 (EG_ACL_ COUNTER_GRP12)180 8.8.71 Ingress aCL c nter group 5 8.8.95 Egress ACL Counter Group 13 (G_ACL_COUNTER_GRP5)174 EG_ACL_COUNTER_GRP13)180 8.8.72 Ingress ACL Counter Group 6 8.8.96 Egress ACL Counter Group 14 (IG_ACL_COUNTER_GRP6)174 (EG_ACL_COUNTER_GRP14)180 8.8.73 Ingres ACL Counter Group 7 8.8.97 Egress ACL Counter Group 15 (G_ACL_COUNTER_GRP7) 174 (EG_ACL_COUNTER_-GRP15)180 88.7 Ingress acl Counter group 8 8.8.98 Clear acl counters (G_ACL_COUNTER_GRP8) 175 CLEAR_ ACL__COUNTERS). 181 8.875 Ingress ACL Counter Group 9 8.8.99 Ingress ACL Rule Vector Lower (G ACL COUNTER GRP9. 175 (G ACL RULE VECTOR LOWE 8.8.76 Ingress ACL Counter Group 10 R) 181 (G_ACL_COUNTER_GRP10) 175 8.8. 100 Ingress ACL Rule vector Upper 8.8.77 Ingress ACL Counter Group 11 (G ACL RULE VECTOR UPPER (G_ACL_COUNTER_GRP11)175 181 8.8.78 Ingress ACL Counter Group 12 8.8.101 Egress ACl Rule Vector Lower (IG_ACL_COUNTER_GRP12)176 (EG ACL RULE VECTOR LOWE 8.8.79 Ingress ACL Counter Group 13 R) .181 (IG_ACL_COUNTER_GRP13)176 8.8.102 Egress ACL Rule Vector Upper 6 AR9341 Highly-Integrated and Feature-Rich 802.11n 2X2 2.4 GHz Soc Atheros Communications, Inc. October 2012 COMPANY CONFIDENTIAL (EG_ ACL_ RULE VECTOR_ UPPE R .181 8.9 MBOX Registers 8.8.103 Ingress ACL Rule TableD Lower 8.9.1 Non-Destructive FIFO Status Query (G_ACL_ RULE_-TABLEO_LOWER (MBOX_ FIFO STATUS)………185 182 8.9.2 Non-Destructive SliC FiFo Status 8.8.104 Ingress ACL Rule Table Upper Query (G_ACL RULE_TABLEO_UPPER) (SLIC_MBOX_FIFO_STATUS)186 182 8.9.3 Mailbox DMA Engine Policy 8.8.105 Ingress ACl Rule tablel Lower (G_ACL_RULE_TABLEL_LOWER Control(mBoX_DMA_Policy 186 182 8.9.4 SLIC Mailbox DMA Engine Policy 8.8.106 Ingress ACl Rule tablel Upper Control (IG_ ACL_ RULE_TABLE1_UPPER) (SLIC_MBOX_DMAPOLICY)187 182 8.9.5 RX DMA De criptors Base Address 8.8.107 Ingress ACL Rule Table2 lower (MBOX_DMA_RX_ DESCRIPTOR (IG_ACL-RULE_TABLE2_LOWER BASE)..…1 …182 89.6 Rx DMA Control 8.8.108 Ingress aCl Rule table2 upper (MBOX_DMA RX_ CONTROL)188 (IG_ACL_RULE_ TABLE2_UPPER) 183 8.9.7 TX DMA Descriptors Base Address (MBOX_DMA_TX_DESCRIPTOR 8.8. 109 Ingress aCl Rule Table3 Lower BASE)…………,, 188 IG_ACL_RULE_TABLE3_LOWER 89.8 TX DMA Control (MBOX_ DMA_TX_CONTROL)189 8.8. 110 Ingress ACL Rule Table3 Upper (G_ACL_RULE_TABLE3_UPPER 8.9.9 SLIC RX DMA Descriptors Base Address 183 (SLIC- DMA RX_ DESCRIPTOR B 8.8.111 Egress ACl Rule table l wer ASE 189 (EG_ ACL RULE- TABLEO LOWE 8.9.10 SLIC RX DMA Control R 183 (SLIC_DMA_ RX CONTROL) 190 8.8. 112 Egress ACL Rule Table0 Upper (EG_ACL_RULE_TABLEO_UPPER) 8.9. 11 SLIC TX DMA Descriptors Base 183 Address (SLIC_DMA_TX_ DESCRIPTOR_B 8.8. 113 Egress ACL Rule Tablel Lower ASE (EG_ACL_ RULE_TABLE1_LOWE R) 184 8.9.12 SLIC TX DMA Control (SLIC DMA TX CONTROL) 191 8.8.114 Egress aCL Rule tablel Upper (EG_ACL_RULE- TABLEL_UPPER) 8.9. 13 Mailbox Fifo status 191 184 (MBOX_FRAME 88.115 Egress ACL Rule table2 Lower 8.9.14 SLIC Mailbox FiFo status (EG_ACL_ RULE- TABLE2_LOWE ( SLIC MBOX FRAME)……191 R) 184 8.9. 15 FIFO Timeout period (FIFO_TIMEOUT) 192 8.8.116 Egress aCl Rule table2 Upper (EG_ACL_RULE-TABLE2_UPPER) 8.9.16 MBOX Related Interrupt Status …184 ( MBOX INT STATUS)…………192 8.8. Egress ACL, Rule Table3 Lower 8.9.I7 SLIC MBOX Related Interrupt (EG_ACL_RULE__TABLE3_LOWE Status R) 184 (SLIC_MBOX_INTSTATUS). 193 8.8.118 Egress ACL Rule table3 Upper 8.9. 18 MBOX Related Interrupt Enables (EG_ ACL RULE_ TABLE3_UPPER (MBOX_ INT ENABLE)……193 Atheros Communications, Inc AR9341 Highly-Integrated and Feature-Rich 802. 11n 2X2 2.4 GHz Soc

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为真正实现 5G 和通信行业的健康发展,中国电信认为 5G 应以业务需求为驱动,以未来 5G 网络架构为目标,针对 5G 发展中的主要挑战,提出中国电信5G 网络演进策略和阶段目标,探索新的 5G 网络建设方案与运营模式,同时积极推动 5G 与垂直行业相结合的业务创新,构筑健壮的 5G 生态圈。在 5G 的创 新驱动下,中国电信将进一步推动“网络智能化、业务生态化、运营智慧化”的内涵向“泛网络智能、广业务生态、精智慧运营”方向发展

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smc-新款减压阀AR10~60.pdf

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2019-09-26 立即下载
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