AR9341 PDF

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Arthors 9341 PDF资料,非常流行的单芯片300M无线路由器解决方案。
PRELIMINARY Pin Descriptions This section contains both a package pinout The following nomenclature is used for signal and tabular listings of the signal descriptions typ The following nomenclature is used for signal names IA Analog input signal nc No connection should be made to I Digital input signal this H Input signals with weak internal l At the end of the signal name, pull-up, to prevent signals from indicates active low signals floating when left open At the end of the signal name IL Input signals with weak internal indicates the positive side of a pull-down, to prevent signals differential signal from floating when left open At the end of the signal name Iyo A digital bidirectional signal indicates the negative side of a differential signal OA An analog output signal O a digital output signal a power or ground signal Atheros Communications, InC. AR9341 Highly-Integrated and Feature-Rich 802. 11n 2X2 2. 4 GHz Soc .3 COMPANY CONFIDENTIAL February 2011 PRELIMINARY Figure 1-1 shows the AR9341 pinout o乏 .Nz 圆图圆圓圓圆圓圓 B1 DDR_DATA_13 ANTB(B57 DDR DATA12【63) (A64 ANTA B2 )VDD_DDR RFIN2GP 1(856 DDR_DATA_11 A4 A63 RFIN2GN 1 AVDD12(B55 DDR_DATA_9 A5 A62 RFOUT2GN_1 B4DDR_CKE_L RFOUT2GP 1(B54 DDR_DQS_1 Ae (A61 AVDD33 B5DDR VREF AVDD12(B53 (A60AVD033 L DDR_A_3 XTALI(B52 VDD12 48) A59 XTALO 7DDR_CK_N SYS_RST_OUT_L(B51 DDR_CK_P A9 B8DDR_A_12 GPI017(B50 DDR_A_11A10 A57GPI016 GPI015(B49 DDR_A_8A11 A56G014 VDD_DDR A12) AR9341 (A55FI012 □[E)DRA6 VDD12(B47] DDR_A_5A13 546PI011 B12)DDR_A_4 DDR_WE_LLA14 GPIO8(815] DDR_CAS_LA15 A52 GPIO7 B14DDR_RAS_L GP06(84 DDR_CS_L A16 A51 GPIO5 B15DDR_BA_0 AVDD12(B43 DDR BA 1 A17 (A50 USB_DP B16)DDR_A_10 USB DM(B42 VDD_DDR A18 A49 AVDD33 B17)DDR_A VDD25(B41 DDR A 1A1g A48 CTRL20 B18)DDR A 2 AVD20(B401 CTRL DDR XPNP A2C (A47 VDD12 B19)VDD33 RBIAS(B39 (A45 VDD 85盏 爸泛 谷 国国国国国国国国国国国国国国国度 曩喜員昌息羹意昌袅薏§ 灵 ms Figure 1-1. Package Pinout(See-Through Top View) 4. AR9341 Highly-Integrated and Feature-Rich 802.11n 2X2 2. 4 GHz Soc Atheros Communications, Inc. February 2011 COMPANY CON FIDENTIAL PRELIMINARY Table 1-1 provides the signal-to-pin relationship information for the ar9341 Table 1-1. Signal to Pin Relationships and descriptions Signal name Pins Type Description General RESET L A23 IH External power on reset with weak pull up SYS RST OUT L B51 od System reset out, open drain, pull up is required XTALI B52 40 MHz or 25 MHz crystal XTALO A59 I/0 When using an external clock, the XTall pin is grounded and AC coupling is recommended for the clock signal to the XTALO pin The internal circuit provides the dc bias of approximately 0.6 V. The peak to peak swing of the external clock can be between 0.6 V to 1. 2 V Larger swing and sharper edge will reduce jitter Radio rFin2Gn O B64 IA Differential RF inputs for 2.4 GHz chain O RFIN2GP 0 A75 IA Use one side for single-ended input RFOUT2GN O B63 OA Differential RF outputs for 2.4 GHz chain 0 RFOUT2GP O A73 OA rFin2Gn 1 A63 la Differential RF inputs for 2.4 GHz chain 1 RFIN2GP 1 B56 IA Use one side for single-ended input RFOUT2Gn 1 A62 OA Differential RF outputs for 2.4 GHz chain 1 RFOUT2GP 1 B54 OA Analog Interface BIASREF B65 a BIASREF voltage is 310 mV; must connect a 6. 19 KU+1% resistor to ground RBIAS B39 Ia BIAS for Ethernet XPABIAS2 0 B60 oa Bias for optional external power amplifier XPABIAS2 1 B59 OA External Switch Control ANTA A64 o External RF switch contro Ant B57 O ANTC B58 ANTD A69 Ethernet switch RXNO B37 IA Ethernet port O receive pair, can be grounded if not used RXPO A41 RXN1 A40 Ia Ethernet port 1 receive pair, can be grounded if not used RXP1 B35 IA Atheros Communications, InC. AR9341 Highly-Integrated and Feature-Rich 802. 11n 2X2 2. 4 GHz Soc.5 COMPANY CONFIDENTIAL February 2011 PRELIMINARY Table 1-1. Signal to Pin Relationships and Descriptions (continued) Signal name Pi Ins Type Description RXN2 B32 Ia Ethernet port 2 receive pair, can be grounded if not used RXP2 A36 IA RXN3 A35 Ethernet port 3 receive pair, can be grounded if not used RXP3 B30 RXN4 A31 Ia Ethernet port 4 receive pair, can be grounded if not used RXP4 B26 IA TXNO B38 Oa Ethernet port O transmit pair, can be left open if not used TXPO A42 OA TXN1 A39 Oa Ethernet port 1 transmit pair, can be left open if not used TXPT B34 OA TXN2 B33 Oa Ethernet port 2 transmit pair, can be left open if not used TXP2 A37 OA TXN3 A34 oa Ethernet port 3 transmit pair, can be left open if not used TXP3 B29 OA TXN4 A32 OA Ethernet port 4 transmit pair, can be left open if not used TXP4 B27 OA External Memory Interface DDR A O B17 o 13-bit external memory address bus DDRA1 A19 O DDR A 2 B18 DdRa3 B6 DDR 4 B12 DDR A5 A13 DDRa 6 B11 DDRA7 B10 ddRa 8 A11 ddra 9 DDRA 10 B16 OO DDR A 11 A10 DDR A 12 DDR BA O B15 O2-bit bank address to indicate which bank the chip is accessing DDR BA 1 A17 DDR CKE L B4 Deactivates the external memory clock when the signal is high DDR CK N BZ o DDR CK P and DDR CK Nare differential clock inputs.All DDR CK P A9 address and control signals timing are related to the crossing of the positive edge of DDR_CK_Pand the negative edge of DDR CK N DDR CS L A16 External memory chip select signal, active low 6 AR9341 Highly-Integrated and Feature-Rich 802.11n 2X2 2. 4 GHz Soc Atheros Communications, Inc. February 2011 COMPANY CON FIDENTIAL PRELIMINARY Table 1-1. Signal to Pin Relationships and Descriptions (continued) Signal Name Pins Type Description DDR CAS L A15 When this signal is asserted it indicates the address is a column address active when the signal is low DDR RAS L B14 When this signal is asserted, it indicates the address is a row address. Active when the signal is low DDR DQM_0 A85 o ddR data mask for data byte 0, 1, 2 and3 DDR DQM_ A7 DDR_DQS_O B74 I/0 DDR data strobe for data byte 0, 1, 2 and 3 DDR DQS 1 I/O DDR VREF B5 I DDR reference level for SSTL signals DDR WE L A14 o When this signal is asserted, it indicates that the following transaction is write. Active when the signal is low DDR DATA O A80 I/0 16-bit external memory data bus DDR DATA 1 B70 I/O DDR DATA 2 A81 I/O DDR DATA 3 B71 I/O DDR DATA 4 A82 I/ DDR DATA 5 B71 I/O DDR DATA 6 B73 I/O DDR DATA 7 A84 I/O DDR daTA 8 B76 I/O DDR dAtA 9 I/O DDR DATA 10 B3 I/O DDR DATA 11 A4 I/O DDR DATA 12 A3 I/O DDR DATA 13 BI DDR DATA 14 A86 I/O DDR DATA 15 B75 I/O Atheros Communications, InC. AR9341 Highly-Integrated and Feature-Rich 802. 11n 2X2 2. 4 GHz SoC COMPANY CONFIDENTIAL February 2011 PRELIMINARY Table 1-1. Signal to Pin Relationships and Descriptions (continued) Signal name Pi Ins Type Description GPIO GPIO B23 t/0 General purpose T/O, programmable, can to be used as JTAG, SPL I2S SLIC, UART LED control GPIO A28 GPIO2 B24 I/O GPIO3 A29 I/O GPIO B25 I/O GPIO5 A51 I/O GPIO B44 I/O GPIO A52 I/O GPIO8 B45 I/O GPIO A53 I/O GPIO10 B46 I/O GPIO11 A54 I/O GPIO12 A55 GPIO13 B48 I/O GPIO14 A56 I/O GPIO]5 B49 1/O GPIO16 A57 I/O GPIO17 B50 I/O GPIO18 B66 I/O GPIO19 A77 I/O GPIO20 B67 I/O GPIO21 A78 I/O GPIO22 B68 O USB USB DM B42 IA/OA USB D-signal; carries USB data to and from the USB 2.0 PHY USB DP A50 IA/OA USB D+ signal; carries USB data to and from the USB 2.0 PHY Regulator Control CTRL DDR XPNP A20 OA External PNP Control. Connect to the base of an external Pnp collector to vdd ddR and emitter to Vld33 cTRL20 A48 Oa External PNP control. Connect to the base of an external PNP collector to avdd20 and emitter to VDD33 Internal Requlator AVDD12 SWREG OUT A26, B21 P 1.2 V switching regulator output see figure 9-1,Output Voltages Regulated by the AR9341, on page 392 AVDD33 SWREG A25,B20 P 3.3 V input to the internal switching regulator AVDD12 SWREG FB B22 Feedback to the internal switching regulator 8. AR9341 Highly-Integrated and Feature-Rich 802.11n 2X2 2.4 GHz Soc Atheros Communications, Inc. February 2011 COMPANY CON FIDENTIAL PRELIMINARY Symbol Pin Description Power AVDD12 A72,A74,A76,B43,B53,B55 Analog 1.2 V supply VDD12 A8, A27, A17, B13, B28, B31, B36, B47, B69 Digital 1.2 V supply AVDD20 B40 Analog 2.0 V supply output from the AR9341 AVDD33 A49,A60,A61,B61,B62 Analog 3. 3 v supply VDD DDR A12,A18,A83,B2 Digital DDR1/DDR2 supply, 1.8V or 2.6V ⅤDD25 A30, A33, A38, A45, A58, A79, B41 Digital 2.5 V supply 7DD33 B19 Digital 3.3 V supply NC A70,A71 No connect Ground pad Exposed Ground Tied to GND; see"Package Dimensions"on Pad page 387 Atheros Communications, InC. AR9341 Highly-Integrated and Feature-Rich 802. 11n 2x2 2. 4 GHz Soc .9 COMPANY CONFIDENTIAL February 2011 PRELIMINARY 10 AR9341 Highly-Integrated and Feature-Rich 802.11n 2X2 2.4 GHz Soc Atheros Communications, Inc. February 2011 COMPANY CON FIDENTIAL

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    afeionline 很值得参考,非常感谢!
    2017-11-29
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    cihyz good非常感谢
    2016-03-31
    回复
    jy03254628 非常好,十分感谢
    2016-03-23
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    lcwjl_jl 非常好,十分感谢
    2015-07-16
    回复
    stone-code 规格书很详细哈 不是那种3页的简介版本
    2015-05-12
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    u010263643 非常好的资料,改路由器,刮CPU必备!
    2015-04-12
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    御临天下 英文资料,很全面。
    2015-03-01
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    yihongli2472gmail 这个对我评估芯片的性能很有帮助,我要这个学习一下
    2014-12-26
    回复
    jkangb 谢谢楼主,项目需要,学习一下。
    2014-09-17
    回复
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