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Altera/Intel FPGA-MAX10手册

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官方的MAX10技术手册

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MAX 10 FPGA Device Architecture

2014.12.15

M10-ARCHITECTURE

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The MAX

10 devices consist of the following:

• Logic array blocks (LABs)

• Analog-to-digital converter (ADC)

• User flash memory (UFM)

• Embedded multiplier blocks

• Embedded memory blocks (M9K)

• Clocks and phase-locked loops (PLL)

• General purpose I/O

• High-speed LVDS I/O

• External memory interfaces

• Configuration flash memory (CFM)

trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as

trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance

of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any

products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,

product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device

specifications before relying on any published information and before placing orders for products or services.

ISO

9001:2008

Registered

www.altera.com

101 Innovation Drive, San Jose, CA 95134

Figure 1: Typical Device Floorplan for MAX 10 Devices

• The amount and location of each block varies in each MAX 10 device.

• Certain MAX 10 devices may not contain a specific block.

Embedded MultipliersEmbedded Memory

PLL

Logic Array Blocks

I/O Banks

PLL

PLL PLL

I/O Banks

Internal Flash

CFM

Clocks

UFM

ADC block

Related Information

• MAX 10 Device Datasheet

Provides more information about specification and performance for MAX 10 devices.

• MAX 10 FPGA Device Overview

Provides more information about maximum resources in MAX 10 devices

Logic Array Block

The LABs are configurable logic blocks that consist of a group of logic resources.

Each LAB consists of the following:

• 16 logic elements (LEs)—smallest logic unit in MAX 10 devices

• LE carry chains—carry chains propagated serially through each LE within a LAB

• LAB control signals—dedicated logic for driving control signals to LEs within a LAB

• Local interconnect—transfers signals between LEs in the same LAB

• Register chains—transfers the output of one LE register to the adjacent LE register in a LAB

Logic Array Block

M10-ARCHITECTURE

2014.12.15

Altera Corporation

MAX 10 FPGA Device Architecture

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Figure 2: LAB Structure of MAX 10 Devices

Direct link

interconnect

from adjacent

block

Direct link

interconnect

to adjacent

block

Row Interconnect

Column

Interconnect

Local Interconnect

LAB

Direct link

interconnect

from adjacent

block

Direct link

interconnect

to adjacent

block

The Quartus

II Compiler places associated logic in a LAB or adjacent LABs, allowing the use of local and

LAB Interconnects

The LAB local interconnect is driven by column and row interconnects and LE outputs in the same LAB.

The direct link connection minimizes the use of row and column interconnects to provide higher

performance and flexibility. The direct link connection enables the neighboring elements from left and

right to drive the local interconnect of a LAB. The elements are:

• LABs

• PLLs

• M9K embedded memory blocks

• embedded multipliers

Each LE can drive up to 48 LEs through local and direct link interconnects.

M10-ARCHITECTURE

2014.12.15

LAB Interconnects

MAX 10 FPGA Device Architecture

Altera Corporation

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Figure 3: LAB Local and Direct Link Interconnects for MAX 10 Devices

LAB

Direct link

interconnect

to right

Direct link interconnect from

right LAB, M9K memory

block, embedded multiplier,

PLL, or IOE output

Direct link interconnect from

left LAB, M9K memory

block, embedded multiplier,

PLL, or IOE output

Local

Interconnect

Direct link

interconnect

to left

LEs

LAB Control Signals

Each LAB contains dedicated logic for driving control signals to its LEs.

The control signals include:

• Two clock signals

• Two clock enable signals

• Two asynchronous clear signals

• One synchronous clear signal

• One synchronous load signal

LAB Control Signals

M10-ARCHITECTURE

2014.12.15

Altera Corporation

MAX 10 FPGA Device Architecture

Send Feedback

Figure 4: LAB-Wide Control Signals for MAX 10 Devices

labclkena1

labclk2labclk1

labclkena2

labclr1

Dedicated

LAB Row

Clocks

Local

Interconnect

Local

Interconnect

Local

Interconnect

Local

Interconnect

syncload

synclr

labclr2

Table 1: Control Signal Descriptions for MAX 10 Devices

Control Signal Description

labclk1

• Each LAB can use two clocks signals. The clock and clock enable signals

of each LAB are linked. For example, any LE in a particular LAB using

the labclk1 signal also uses the labclkena1 signal.

• If the LAB uses both the rising and falling edges of a clock, it also uses

both LAB-wide clock signals.

• The LAB row clocks [5..0] and LAB local interconnect generate the

LAB-wide clock signals. The MultiTrack interconnect inherent low skew

allows clock and control signal distribution in addition to data distribu‐

tion.

labclk2

labclkena1

• Each LAB can use two clock enable signals. The clock and clock enable

signals of each LAB are linked. For example, any LE in a particular LAB

using the labclk1 signal also uses the labclkena1 signal.

• Deasserting the clock enable signal turns off the LAB-wide clock signal.

labclkena2

labclr1 Asynchronous clear signals:

• LAB-wide control signals that control the logic for the clear signal of the

• The LE directly supports an asynchronous clear function.

labclr2

syncload Synchronous load and synchronous clear signals:

• Can be used for implementing counters and other functions

• LAB-wide control signals that affect all registers in the LAB

synclr

M10-ARCHITECTURE

2014.12.15

LAB Control Signals

MAX 10 FPGA Device Architecture

Altera Corporation

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