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Taiwan Semiconductor Manufacturing Co., LTD
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The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
Ver. Eff_Date ECN No. Author Change Description
0.1
10-18-06
C.L. ChuA
Original
Revisor :
Revising
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Title
TSMC 0.16 UM CMOS HIGH VOLTAGE
MIXED SIGNAL BASED LDMOS 1P6M
SALICIDE 1.8/5/32V DESIGN RULE
Document No. :
Contents : 148
Attach. : 0
Total : 148
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Review
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PLEASE RETURN OLD VERSION SPEC TO DC
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tsmc
Taiwan Semiconductor Manufacturing Co., LTD
Document No. T-018-CV-DR-005 Ver. 0.2 Page 1
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
TSMC 0.16 UM CMOS HIGH VOLTAGE MIXED SIGNAL BASED
LDMOS 1P6M SALICIDE 1.8/5/32V DESIGN RULE
tsmc
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tsmc
Taiwan Semiconductor Manufacturing Co., LTD
Document No. T-018-CV-DR-005 Ver. 0.2 Page 2
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
Contents
1. INTRODUCTION .........................................................................................................................................................4
1.1 OVERVIEW..............................................................................................................................................................4
1.2 REFERENCE DOCUMENTATION.................................................................................................................................5
1.3 USER GUIDELINE ....................................................................................................................................................6
2 KEY PROCESS SEQUENCE..........................................................................................................................................9
2.1 MASK INFORMATION, KEY PROCESS SEQUENCE, AND CAD LAYERS .........................................................................9
2.2 SPECIAL RECOGNITION CAD LAYER SUMMARY ......................................................................................................12
3 TECHNOLOGY OVERVIEW .........................................................................................................................................13
3.1 SEMICONDUCTOR PROCESS ..................................................................................................................................13
3.1.1 Front-End Features .....................................................................................................................................13
3.1.2 Back-End Features......................................................................................................................................15
3.2 POWER SUPPLY OF DEVICES.................................................................................................................................16
3.3 DEVICE TRUTH TABLE ...........................................................................................................................................18
3.4 HIGH VOLTAGE (32V) MOS DEVICE FEATURES .....................................................................................................23
3.4.1 HV MOS Device List and Spec ...................................................................................................................23
3.4.2 High Voltage (32V) MOS Device Dimension....................................................................................................24
3.4.3 Asymmetric HVNMOS device layout..............................................................................................................25
3.4.4 Asymmetric HVPMOS device layout ..............................................................................................................26
3.4.5 Isolated HVNMOS device layout ......................................................................................................................27
3.4.6 Symmetric HVNMOS device layout..............................................................................................................28
3.4.7 Symmetric HVPMOS device layout................................................................................................................29
3.5 DEVICE ISOLATION RULES AND GUIDELINES ...........................................................................................................30
3.5.1 HV Device Isolation.....................................................................................................................................30
3.5.2 LV Device Isolation......................................................................................................................................33
3.5.3 .......................................................................................................................... 35Boundary for LV and HV Devices
3.5.4 3.5.4 Product Product Labels and Logo RulesLabels and Logo Rules
4 LAYOUT RULES ...........................................................................................................................................................38
4.1 LAYOUT RULE CONVENTIONS ................................................................................................................................38
4.2 SPECIAL GEOMETRIES USED IN PHYSICAL DESIGN RULES ......................................................................................39
4.3 DEFINITION OF THE LAYOUT GEOMETRICAL TERMINOLOGY......................................................................................40
4.4 LAYOUT RULES AND GUIDELINES (1.8V/5V/32V) ...................................................................................................42
4.4.1 N+ Buried Layer (NBL) Layout Rules (112) ................................................................................................42
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The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
4.4.2 Gate Oxide and Diffusion (OD) Layout Rules (120)....................................................................................43
4.4.3 High Voltage N-Well (HVNW) Layout Rules (19A).........................................................................................50
4.4.4 High Voltage Device Area (HV) Layout Rules (12A)......................................................................................54
4.4.5 N-Well (NW) Layout Rules............................................................................................................................56
4.4.6 Thick Oxide (OD2) Layout Rules (132).........................................................................................................60
4.4.7 Poly (PO) Layout Rules (130).......................................................................................................................62
4.4.8 Poly Resistor Guideline.................................................................................................................................69
4.4.9 N+ Source/Drain Ion Implantation (NP) Layout Rules (198).........................................................................71
4.4.10 P+ Source/Drain Ion Implantation (PP) Layout Rules (197).......................................................................74
4.4.11 High Resistor Implant (HRI) Layout Rules (133) (Optional) .......................................................................77
4.4.12 ESD Implantation (ESD) Layout Rules (110) (Optional).............................................................................78
4.4.13 Resist Protection Oxide (RPO) Layout Rules (155)....................................................................................80
4.4.14 Contact (CO) Layout Rules (156) ...............................................................................................................83
4.4.15 Metal 1 (M1) Layout Rules (160) ................................................................................................................87
4.4.16 VIA1 to VIA4 (VIAx) Layout Rules (178,179,173,174)................................................................................91
4.4.17 Metal-2 to Metal-5 (Mx) Rules (180,181,184,185)......................................................................................93
4.4.18 CTM Layout Rules (182) (Optional)............................................................................................................95
4.4.19 VIA5 Layout Rules (175).............................................................................................................................96
4.4.20 Metal-6 Layout Rules (186).........................................................................................................................98
4.4.21 Passivation & Polyimide Rule (107 & 009) ...............................................................................................100
4.4.22 Metal Fuse Rule........................................................................................................................................100
4.4.23 Seal-Ring Rule..........................................................................................................................................101
4.4.24 Antenna Effect Prevent.............................................................................................................................103
4.4.25 Stress Release Rule..................................................................................................................................105
4.4.26 SRAM Guideline........................................................................................................................................118
4.4.27 Planar capacitor Emb-SRAM Rule............................................................................................................119
4.4.28 Note for High Reliability Applications ........................................................................................................120
5 ESD AND LATCH-UP DESIGN RULES AND GUIDELINES .....................................................................................121
5.1 LATCH UP AND GUARD RING LAYOUT RULES FOR HV DEVICE................................................................................121
5.2 HV ESD RULES AND GUIDELINES .......................................................................................................................123
5.3 LV I/O ESD PROTECTION CIRCUIT DESIGN AND LAYOUT GUIDELINE .......................................................................129
5.4 LAYOUT GUIDELINE FOR LATCH-UP PREVENTION ....................................................................................................142
6 GUIDELINE AND RULES FOR EM ............................................................................................................................144
6.1 CURRENT DENSITY SPECIFICATION......................................................................................................................144
APPENDIX A REVISION HISTORY...............................................................................................................................147
A.1 FROM VERSION 0.1 TO VERSION 0.2........................................................................................................................147
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Document No. T-018-CV-DR-005 Ver. 0.2 Page 4
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
1. Introduction
1.1 Overview
This document provides all the rules and reference information for the design and layout of integration circuits
using the TSMC 0.18um Low Power CMOS High Voltage Mixed-Signal 1P6M (single poly, 6 metal layers),
salicide, Al technology. These rules and information apply to high voltage applications: 1.8/5/32V.
“1.8/5/32V” is a high-voltage product for performance applications with a 1.8V core, 5V I/O’s and 32V
high voltage design. 2.5V or 3.3V devices are not offered in this process.
This design rules (or layout rules) are defined with the dimension on wafer. The differences of the feature size
between on-mask pattern and on-silicon pattern are adjusted by CAD (Computer- Aided Design) bias.
This manual contains generic and high voltage rules.
(1) The generic low voltage part (1.8V & 5V, brief as “LV”), which is aligned with TSMC’s 0.18um 1.8V/3.3V
1P6M design rule (Document No.: T-018-LO-DR-001) and 0.18um 1.8V/5V 1P6M design rule (Document
No.: T-018-LO-DR-011). Please always refer to the most updated design rule document.
(2) The high voltage part (32V, brief as “HV”) includes the high voltage devices related layout rules.
For the mixed-signal application, please refer to the TSMC’s 0.18um Mixed-Signal 1.8V/3.3V 1P6M design
rule (Document No.: T-018-MM-DR-001). However, only HRI resistors and MIM capacitor are supported in this
HV process.
To prevent circuit fail, only the following devices are allowed to apply with high voltage bias (greater than 5V):
a) HVMOS; b) HVNW/HVPW diodes and c) HVPW/HVPW_NBL diodes. Please do not apply the high voltage
bias (greater than 5V) on those logic/mixed-signal devices (called as LV devices). Such connection would
introduce circuit function failure or reliability concern. If you have any special requirement or problem, please
consult TSMC in advance.
