Verilog HDL QUICK
REFERENCE CARD
Revision 2.1
() Grouping [ ] Optional
{} Repeated | Alternative
bold As is CAPS User Identifier
1. MODULE
module MODID[({PORTID,})];
[input | output | inout [range] {PORTID,};]
[{declaration}]
[{parallel_statement}]
[specify_block]
endmodule
range ::= [constexpr : constexpr]
2. DECLARATIONS
parameter {PARID = constexpr,};
wire | wand | wor [range] {WIRID,};
reg [range] {REGID [range],};
integer {INTID [range],};
time {TIMID [range],};
real {REALID,};
realtime {REALTIMID,};
event {EVTID,};
task TASKID;
[{input | output | inout [range] {ARGID,};}]
[{declaration}]
begin
[{sequential_statement}]
end
endtask
function [range] FCTID;
{input [range] {ARGID,};}
[{declaration}]
begin
[{sequential_statement}]
end
endfunction
3. PARALLEL STATEMENTS
assign [(strength1, strength0)] WIRID = expr;
initial sequential_statement
always sequential_statement
MODID [#({expr,})] INSTID
([{expr,} | {.PORTID(expr),}]);
GATEID [(strength1, strength0)] [#delay]
[INSTID] ({expr,});
defparam {HIERID = constexpr,};
strength ::= supply | strong | pull | weak | highz
delay ::= number | PARID | ( expr [, expr [, expr]] )
4. GATE PRIMITIVES
and (out, in
1
, ..., in
N
); nand (out, in
1
, ..., in
N
);
or (out, in
1
, ..., in
N
); nor (out, in
1
, ..., in
N
);
xor (out, in
1
, ..., in
N
); xnor (out, in
1
, ..., in
N
);
buf (out
1
, ..., out
N,
in); not (out
1
, ..., out
N,
in);
bufif0 (out, in, ctl); bufif1 (out, in, ctl);
notif0 (out, in, ctl); notif1 (out, in, ctl);
pullup (out); pulldown (out);
[r]pmos (out, in, ctl);
[r]nmos (out, in, ctl);
[r]cmos (out, in, nctl, pctl);
[r]tran (inout, inout);
[r]tranif1 (inout, inout, ctl);
[r]tranif0 (inout, inout, ctl);
5. SEQUENTIAL STATEMENTS
;
begin[: BLKID
[{declaration}]]
[{sequential_statement}]
end
if (expr) sequential_statement
[else sequential_statement]
case | casex | casez (expr)
[{{expr,}: sequential_statement}]
[default: sequential_statement]
endcase
forever sequential_statement
repeat (expr) sequential_statement
while (expr) sequential_statement
for (lvalue = expr; expr; lvalue = expr)
sequential_statement
#(number | (expr)) sequential_statement
@ (event [{or event}]) sequential_statement
lvalue [<]= [#(number | (expr))] expr;
lvalue [<]= [@ (event [{or event}])] expr;
wait (expr) sequential_statement
-> EVENTID;
fork[: BLKID
[{declaration}]]
[{sequential_statement}]
join
TASKID[({expr,})];
disable BLKID | TASKID;
assign lvalue = expr;
deassign lvalue;
lvalue ::=
ID[range] | ID[expr] | {{lvalue,}}
event ::= [posedge | negedge] expr
6. SPECIFY BLOCK
specify_block ::= specify
{specify_statement}
endspecify
6.1. SPECIFY BLOCK STATEMENTS
specparam {ID = constexpr,};
(terminal => terminal) = path_delay;
((terminal,} *> {terminal,}) = path_delay;
if (expr) (terminal [+|-]=> terminal) = path_delay;
if (expr) ({terminal,} [+|-]*> {terminal,}) =
path_delay;
[if (expr)] ([posedge|negedge] terminal =>
(terminal [+|-]: expr)) = path_delay;
[if (expr)] ([posedge|negedge] terminal *>
({terminal,} [+|-]: expr)) = path_delay;
$setup(tevent, tevent, expr [, ID]);
$hold(tevent, tevent, expr [, ID]);
$setuphold(tevent, tevent, expr, expr [, ID]);
$period(tevent, expr [, ID]);
$width(tevent, expr, constexpr [, ID]);
$skew(tevent, tevent, expr [, ID]);
$recovery(tevent, tevent, expr [, ID]);
tevent ::= [posedge | negedge] terminal
[&&& scalar_expr]
path_delay ::=
expr | (expr, expr [, expr [, expr, expr, expr]])
terminal ::= ID[range] | ID[expr]
© 1995-1998 Qualis Design Corporation
© 1995-1998 Qualis Design Corporation. Permission to
reproduce and distribute strictly verbatim copies of this
document in whole is hereby granted.
See reverse side for additional information.
© 1995-1998 Qualis Design Corporation