State Machine - |sdram_wr|op_status
Name op_status.OP_SINGLE_WRITE_OVER op_status.OP_SINGLE_WRITE op_status.OP_SINGLE_READ_OVER op_status.OP_SINGLE_READ op_status.OP_IDLE op_status.OP_INIT
op_status.OP_INIT 0 0 0 0 0 0
op_status.OP_IDLE 0 0 0 0 1 1
op_status.OP_SINGLE_READ 0 0 0 1 0 1
op_status.OP_SINGLE_READ_OVER 0 0 1 0 0 1
op_status.OP_SINGLE_WRITE 0 1 0 0 0 1
op_status.OP_SINGLE_WRITE_OVER 1 0 0 0 0 1
State Machine - |sdram_wr|sdram:u1|state
Name state.WAIT_STB_S_LOW state.WAIT_ACK_R_HIGH state.OVER state.WRITE state.READ state.ACTIVE state.LOAD_MODE_REGISTER state.AUTO_REFRESH state.PRECHARGE state.NOP_DELAY state.IDLE state.DELAY
state.DELAY 0 0 0 0 0 0 0 0 0 0 0 0
state.IDLE 0 0 0 0 0 0 0 0 0 0 1 1
state.NOP_DELAY 0 0 0 0 0 0 0 0 0 1 0 1
state.PRECHARGE 0 0 0 0 0 0 0 0 1 0 0 1
state.AUTO_REFRESH 0 0 0 0 0 0 0 1 0 0 0 1
state.LOAD_MODE_REGISTER 0 0 0 0 0 0 1 0 0 0 0 1
state.ACTIVE 0 0 0 0 0 1 0 0 0 0 0 1
state.READ 0 0 0 0 1 0 0 0 0 0 0 1
state.WRITE 0 0 0 1 0 0 0 0 0 0 0 1
state.OVER 0 0 1 0 0 0 0 0 0 0 0 1
state.WAIT_ACK_R_HIGH 0 1 0 0 0 0 0 0 0 0 0 1
state.WAIT_STB_S_LOW 1 0 0 0 0 0 0 0 0 0 0 1
State Machine - |sdram_wr|sdram:u1|old_state
Name old_state.WAIT_STB_S_LOW old_state.WAIT_ACK_R_HIGH old_state.OVER old_state.WRITE old_state.READ old_state.ACTIVE old_state.LOAD_MODE_REGISTER old_state.AUTO_REFRESH old_state.PRECHARGE old_state.NOP_DELAY old_state.DELAY old_state.IDLE
old_state.IDLE 0 0 0 0 0 0 0 0 0 0 0 0
old_state.DELAY 0 0 0 0 0 0 0 0 0 0 1 1
old_state.NOP_DELAY 0 0 0 0 0 0 0 0 0 1 0 1
old_state.PRECHARGE 0 0 0 0 0 0 0 0 1 0 0 1
old_state.AUTO_REFRESH 0 0 0 0 0 0 0 1 0 0 0 1
old_state.LOAD_MODE_REGISTER 0 0 0 0 0 0 1 0 0 0 0 1
old_state.ACTIVE 0 0 0 0 0 1 0 0 0 0 0 1
old_state.READ 0 0 0 0 1 0 0 0 0 0 0 1
old_state.WRITE 0 0 0 1 0 0 0 0 0 0 0 1
old_state.OVER 0 0 1 0 0 0 0 0 0 0 0 1
old_state.WAIT_ACK_R_HIGH 0 1 0 0 0 0 0 0 0 0 0 1
old_state.WAIT_STB_S_LOW 1 0 0 0 0 0 0 0 0 0 0 1
State Machine - |sdram_wr|sdram:u1|op_status
Name op_status.OP_SINGLE_WRITE op_status.OP_SINGLE_READ op_status.OP_AUTO_REFRESH op_status.OP_IDLE op_status.OP_INIT
op_status.OP_INIT 0 0 0 0 0
op_status.OP_IDLE 0 0 0 1 1
op_status.OP_AUTO_REFRESH 0 0 1 0 1
op_status.OP_SINGLE_READ 0 1 0 0 1
op_status.OP_SINGLE_WRITE 1 0 0 0 1
State Machine - |sdram_wr|sdram:u1|command_lst[6]
Name command_lst[6].WAIT_STB_S_LOW command_lst[6].WAIT_ACK_R_HIGH command_lst[6].OVER command_lst[6].WRITE command_lst[6].READ command_lst[6].ACTIVE command_lst[6].LOAD_MODE_REGISTER command_lst[6].IDLE command_lst[6].PRECHARGE command_lst[6].NOP_DELAY command_lst[6].DELAY command_lst[6].AUTO_REFRESH
command_lst[6].AUTO_REFRESH 0 0 0 0 0 0 0 0 0 0 0 0
command_lst[6].DELAY 0 0 0 0 0 0 0 0 0 0 1 1
command_lst[6].NOP_DELAY 0 0 0 0 0 0 0 0 0 1 0 1
command_lst[6].PRECHARGE 0 0 0 0 0 0 0 0 1 0 0 1
command_lst[6].IDLE 0 0 0 0 0 0 0 1 0 0 0 1
command_lst[6].LOAD_MODE_REGISTER 0 0 0 0 0 0 1 0 0 0 0 1
command_lst[6].ACTIVE 0 0 0 0 0 1 0 0 0 0 0 1
command_lst[6].READ 0 0 0 0 1 0 0 0 0 0 0 1
command_lst[6].WRITE 0 0 0 1 0 0 0 0 0 0 0 1
command_lst[6].OVER 0 0 1 0 0 0 0 0 0 0 0 1
command_lst[6].WAIT_ACK_R_HIGH 0 1 0 0 0 0 0 0 0 0 0 1
command_lst[6].WAIT_STB_S_LOW 1 0 0 0 0 0 0 0 0 0 0 1
State Machine - |sdram_wr|sdram:u1|command_lst[5]
Name command_lst[5].WAIT_STB_S_LOW command_lst[5].WAIT_ACK_R_HIGH command_lst[5].OVER command_lst[5].WRITE command_lst[5].READ command_lst[5].ACTIVE command_lst[5].LOAD_MODE_REGISTER command_lst[5].AUTO_REFRESH command_lst[5].PRECHARGE command_lst[5].IDLE command_lst[5].DELAY command_lst[5].NOP_DELAY
command_lst[5].NOP_DELAY 0 0 0 0 0 0 0 0 0 0 0 0
command_lst[5].DELAY 0 0 0 0 0 0 0 0 0 0 1 1
command_lst[5].IDLE 0 0 0 0 0 0 0 0 0 1 0 1
command_lst[5].PRECHARGE 0 0 0 0 0 0 0 0 1 0 0 1
command_lst[5].AUTO_REFRESH 0 0 0 0 0 0 0 1 0 0 0 1
command_lst[5].LOAD_MODE_REGISTER 0 0 0 0 0 0 1 0 0 0 0 1
command_lst[5].ACTIVE 0 0 0 0 0 1 0 0 0 0 0 1
command_lst[5].READ 0 0 0 0 1 0 0 0 0 0 0 1
command_lst[5].WRITE 0 0 0 1 0 0 0 0 0 0 0 1
command_lst[5].OVER 0 0 1 0 0 0 0 0 0 0 0 1
command_lst[5].WAIT_ACK_R_HIGH 0 1 0 0 0 0 0 0 0 0 0 1
command_lst[5].WAIT_STB_S_LOW 1 0 0 0 0 0 0 0 0 0 0 1
State Machine - |sdram_wr|sdram:u1|command_lst[4]
Name command_lst[4].WAIT_STB_S_LOW command_lst[4].WAIT_ACK_R_HIGH command_lst[4].OVER command_lst[4].WRITE command_lst[4].READ command_lst[4].ACTIVE command_lst[4].LOAD_MODE_REGISTER command_lst[4].IDLE command_lst[4].PRECHARGE command_lst[4].NOP_DELAY command_lst[4].DELAY command_lst[4].AUTO_REFRESH
command_lst[4].AUTO_REFRESH 0 0 0 0 0 0 0 0 0 0 0 0
command_lst[4].DELAY 0 0 0 0 0 0 0 0 0 0 1 1
command_lst[4].NOP_DELAY 0 0 0 0 0 0 0 0 0 1 0 1
command_lst[4].PRECHARGE 0 0 0 0 0 0 0 0 1 0 0 1
command_lst[4].IDLE 0 0 0 0 0 0 0 1 0 0 0 1
command_lst[4].LOAD_MODE_REGISTER 0 0 0 0 0 0 1 0 0 0 0 1
command_lst[4].ACTIVE 0 0 0 0 0 1 0 0 0 0 0 1
command_lst[4].READ 0 0 0 0 1 0 0 0 0 0 0 1
command_lst[4].WRITE 0 0 0 1 0 0 0 0 0 0 0 1
command_lst[4].OVER 0 0 1 0 0 0 0 0 0 0 0 1
command_lst[4].WAIT_ACK_R_HIGH 0 1 0 0 0 0 0 0 0 0 0 1
command_lst[4].WAIT_STB_S_LOW 1 0 0 0 0 0 0 0 0 0 0 1
State Machine - |sdram_wr|sdram:u1|command_lst[3]
Name command_lst[3].WAIT_STB_S_LOW command_lst[3].WAIT_ACK_R_HIGH command_lst[3].OVER command_lst[3].WRITE command_lst[3].READ command_lst[3].ACTIVE command_lst[3].LOAD_MODE_REGISTER command_lst[3].AUTO_REFRESH command_lst[3].PRECHARGE command_lst[3].NOP_DELAY command_lst[3].IDLE command_lst[3].DELAY
command_lst[3].DELAY 0 0 0 0 0 0 0 0 0 0 0 0
command_lst[3].IDLE 0 0 0 0 0 0 0 0 0 0 1 1
command_lst[3].NOP_DELAY 0 0 0 0 0 0 0 0 0 1 0 1
command_lst[3].PRECHARGE 0 0 0 0 0 0 0 0 1 0 0 1
command_lst[3].AUTO_REFRESH 0 0 0 0 0 0 0 1 0 0 0 1
command_lst[3].LOAD_MODE_REGISTER 0 0 0 0 0 0 1 0 0 0 0 1
command_lst[3].ACTIVE 0 0 0 0 0 1 0 0 0 0 0 1
command_lst[3].READ 0 0 0 0 1 0 0 0 0 0 0 1
command_lst[3].WRITE 0 0 0 1 0 0 0 0 0 0 0 1
command_lst[3].OVER 0 0 1 0 0 0 0 0 0 0 0 1
command_lst[3].WAIT_ACK_R_HIGH 0 1 0 0 0 0 0 0 0 0 0 1
command_lst[3].WAIT_STB_S_LOW 1 0 0 0 0 0 0 0 0 0 0 1
State Machine - |sdram_wr|sdram:u1|command_lst[2]
Name command_lst[2].WAIT_STB_S_LOW command_lst[2].WAIT_ACK_R_HIGH command_lst[2].OVER command_lst[2].WRITE command_lst[2].READ command_lst[2].ACTIVE command_lst[2].LOAD_MODE_REGISTER command_lst[2].AUTO_REFRESH command_lst[2].IDLE command_lst[2].NOP_DELAY command_lst[2].DELAY command_lst[2].PRECHARGE
command_lst[2].PRECHARGE 0 0 0 0 0 0 0 0 0 0 0 0
command_lst[2].DELAY 0 0 0 0 0 0 0 0 0 0 1 1
command_lst[2].NOP_DELAY 0 0 0 0 0 0 0 0 0 1 0 1
command_lst[2].IDLE 0 0 0 0 0 0 0 0 1 0 0 1
command_lst[2].AUTO_REFRESH 0 0 0 0 0 0 0 1 0 0 0 1
command_lst[2].LOAD_MODE_REGISTER 0 0 0 0 0 0 1 0 0 0 0 1
command_lst[2].ACTIVE 0 0 0 0 0 1 0 0 0 0 0 1
command_lst[2].READ 0 0 0 0 1 0 0 0 0 0 0 1
command_lst[2].WRITE 0 0 0 1 0 0 0 0 0 0 0 1
command_lst[2].OVER 0 0 1 0 0 0 0 0 0 0 0 1
command_lst[2].WAIT_ACK_R_HIGH 0 1 0 0 0 0 0 0 0 0 0 1
command_lst[2].WAIT_STB_S_LOW 1 0 0 0 0 0 0 0 0 0 0 1
State Machine - |sdram_wr|sdram:u1|command_lst[1]
Name command_lst[1].WAIT_STB_S_LOW command_lst[1].WAIT_ACK_R_HIGH command_lst[1].OVER command_lst[1].WRITE command_lst[1].READ command_lst[1].ACTIVE command_lst[1].LOAD_MODE_REGISTER command_lst[1].AUTO_REFRESH command_lst[1].PRECHARGE command_lst[1].IDLE command_lst[1].DELAY command_lst[1].NOP_DELAY
command_lst[1].NOP_DELAY 0 0 0 0 0 0 0 0 0 0 0 0
command_lst[1].DELAY 0 0 0 0 0 0 0 0 0 0 1 1
command_lst[1].IDLE 0 0 0 0 0 0 0 0 0 1 0 1
command_lst[1].PRECHARGE 0 0 0 0 0 0 0 0 1 0 0 1
command_lst[1].AUTO_REFRESH 0 0 0 0 0 0 0 1 0 0 0 1
command_lst[1].LOAD_MODE_REGISTER 0 0 0 0 0 0 1 0 0 0 0 1
command_lst[1].ACTIVE 0 0 0 0 0 1 0 0 0 0 0 1
command_lst[1].READ 0 0 0 0 1 0 0 0 0 0 0 1
command_lst[1].WRITE 0 0 0 1 0 0 0 0 0 0 0 1
command_lst[1].
example.zip_FPGA 例子_fpga 开发板_fpga 源码_fpga开发板源码_vhdl example
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2022-07-15
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example.zip_FPGA 例子_fpga 开发板_fpga 源码_fpga开发板源码_vhdl example （2734个子文件） 
_info 20KB _vmake 26B sdram_wr_global_asgn_op.abo 5.86MB sdram_wr_global_asgn_op.abo 5.86MB sdram_wr_global_asgn_op.abo 1.2MB sdram_wr_global_asgn_op.abo 954KB sdram_wr_global_asgn_op.abo 899KB sdram_wr_global_asgn_op.abo 888KB verilog.asm 1.8MB verilog.asm 979KB verilog.asm 978KB verilog.asm 917KB verilog.asm 888KB verilog.asm 887KB verilog.asm 804KB verilog.asm 775KB verilog.asm 744KB verilog.asm 579KB verilog.asm 573KB verilog.asm 502KB verilog.asm 496KB verilog.asm 458KB verilog.asm 300KB verilog.asm 281KB verilog.asm 253KB verilog.asm 239KB verilog.asm 230KB verilog.asm 223KB verilog.asm 222KB verilog.asm 197KB verilog.asm 160KB verilog.asm 160KB verilog.asm 159KB verilog.asm 149KB verilog.asm 144KB verilog.asm 143KB verilog.asm 139KB verilog.asm 136KB verilog.asm 126KB verilog.asm 115KB verilog.asm 114KB verilog.asm 114KB verilog.asm 98KB verilog.asm 97KB verilog.asm 88KB verilog.asm 84KB verilog.asm 79KB verilog.asm 75KB verilog.asm 69KB verilog.asm 67KB verilog.asm 63KB verilog.asm 52KB verilog.asm 52KB verilog.asm 51KB verilog.asm 51KB verilog.asm 50KB verilog.asm 50KB verilog.asm 50KB verilog.asm 48KB verilog.asm 47KB verilog.asm 46KB verilog.asm 46KB verilog.asm 45KB verilog.asm 39KB verilog.asm 38KB verilog.asm 37KB verilog.asm 37KB verilog.asm 36KB verilog.asm 35KB verilog.asm 34KB verilog.asm 30KB verilog.asm 29KB verilog.asm 28KB verilog.asm 27KB verilog.asm 27KB verilog.asm 25KB verilog.asm 23KB verilog.asm 21KB verilog.asm 21KB verilog.asm 21KB verilog.asm 20KB verilog.asm 19KB verilog.asm 19KB verilog.asm 18KB verilog.asm 18KB verilog.asm 18KB verilog.asm 18KB verilog.asm 17KB verilog.asm 16KB verilog.asm 16KB verilog.asm 16KB verilog.asm 16KB verilog.asm 16KB verilog.asm 16KB verilog.asm 15KB verilog.asm 15KB verilog.asm 15KB verilog.asm 14KB verilog.asm 14KB verilog.asm 14KB共 2734 条
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