MT7621 datasheet

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Ralink MT7621 DATASHEET A MEDIATEK COMPANY Table of contents OVERVIEW 看自音看香看垂香 FEATURES FUNCTIONAL BLOCK DIAGRAM.mmmm ORDERING INFORMATION 22223 TABLE OF CONTENTSmmmmmmm.. 1. MAIN FEATURES , 2. PINS 1看。看。香看看看看。音。D。香 ………6 2.1 TFBGA(11.7 13.6 MM)347 BALL PACKAGE DIAGRAM 211 BALL MAP( TOP VIEW)…,,,,…,…… 2.3 PIN DESCRIPTIONS(TFBGA 2 4 PIN SHARING SCHEMES ·······,·····,·.·, 2. 4. 1 GPlO pin share scheme 14 2. 4. 2 UART pin share scheme 15 2.4.3 RGMll pin share schemes 16 2.4.4 WDT RST MODE pin share scheme 16 2.4.5 PERST N pin share scheme 16 2.4.6 MDC/MD/O pin share scheme: 16 2.4.7 NAND/SDXC/SPI pin share scheme 17 2.4.8 XM// PHY/ MAC Pin Mapping 2.5 BOOTSTRAPPING PINS DESCRIPTION 翻重看面B 21 3. MAXIMUM RATINGS AND OPERATING CONDITIONS∴………………………22 3. 1 ABSOLUTE MAXIMUM RATINGS ,22 3.2 MAXIMUM TEMPERATURES灬…………… ....::::::.::..:::.:.::.:::: 3. 3 OPERATING CONDITIONS 22 3. 4 THERMAL CHARACTERISTICS 3. 5 STORAGE CONDITIONS 3. 6 EXTERNAL XTAL SPECFICATION 3.7 DC ELECTRICAL CHARACTERISTICS(TBU) 23 3. 8 AC ELECTRICAL CHARACTERISTICS 24 3.8.1 DDR SDRAM interface 382RGM∥ nterface 26 38.3M∥ nterface(25Mh) 3.8.4 RvMll Interface(PHy Mode Mll Timing)(25 Mhz) 28 3.8.5 SP/ Interface 3.8.6/'S interface. 3.8.7 PCM interface 3. 8 /2C Interface 31 A 3.8.9 SD/O Interface 3. 8. 10 NAND Flash Interface Samsung Compatibe/ Device .33 3.8. 11 Power On Sequence 36 3. 9 PACKAGE PHYSICAL DIMENSIONS 37 3.9.1 TFBGA(11.7mmx13.6mm)387 balls…,…,…,…,…, 37 3.9. 2 Package Diagram Key 垂面 I..I......8.8.I 3.9.3 MT7621 N/A marking DSMT7621 V.0.2 Prelimanary Page 3 of 43 Ralink MT7621 DATASHEET A MEDIATEK COMPANY 3. 9. 4 Reflow profile guideline 1·" 4. ABBREVIATIONS 40 5. REVISION HISTORY DSMT7621 V.0.2 Prelimanary Page 4 of 43 Ralink MT7621 DATASHEET A MEDIATEK COMPANY 1. Main Features The following table covers the main features offered by the MT7621A. Overall, the Mt7621A supports the requirements of an high-level AP/router, and a number of interfaces together with a large maximum raM capacity. Features MT7621A CPU MIPS1004Kc(880 MHZ) I-Cache, D-Cache 32 KB, 32 KB L2 Cache 256KB HNAT/HQoS HNAT 2 Gbps forwarding Memory DRAM Controller 16b DDR2 128 MB, 800 Mbps DDR3 256 MB, 1200 Mbps NAND Small page 512Byte(max 512M bit Large page 2Kbyte(max 8G bit SPI Flash B addr mode(max 128Mbit 4B addr mode(max 512Mbit) SD SD-XC(class 10) PCle USB 3.0 USB 2.0 2 Switch 5p GSW+RGM(1) 2S PCM 12C 1111 SPDIF-TX UART Lite JTAG 1 Package TFBGA387-117 mmx 13.6 mm Table 1-1 Main features DSMT7621 V.0.2 Prelimanary Page 5 of 43 Ralink MT7621 DATASHEET A MEDIATEK COMPANY 2 Pins 2.1 TFBGA (11.7 mm x 13.6 mm) 347 Ball Package Diagram 2.1.1 Ball Map(Top view) 18 A GND RDQ3 RDQ RDQ12 RDQSO GND RDQ2 RAZ VE RCKE GND B REXTDN RDQ5 RDQ1 RDQ10 RDQMO RDQS1RDQSO RDQM1 RDQ13 RDQ11 GNDRDQ4RA13 RODT RCS_ RA5 RBA1 RAl c ND_D6 RDQ7 GND RDQ14GNDEDQS1 RDQ15 RCLK RDQ9 RDQO RDQ5 GND RRAS RCASRBAO RA14RA11 D D4 ND D5 ND D7 GND GND DVDD D DVDD D DDR3RS DVDD D GND RCLK GND DRIORA9 RA2 DRIODRIO RA12 RAS RAt D DVDD DDVDD D AVDD3s E ND D2 ND D1 ND D3 GND GND GND ND RAZ E DRIO DRIO GNDRA: RAO RA4 MEMP TP ME TN_ME MPLL MPLL DVDD D DVDD D AVSS33 F NDRB- ND Do IND_RE- ND WP IGND GND DVODK DVDDK GND DRIO DRIO-MEMP GND DVDD33 JTCLK TRST N ND CS ND_CLE ND ND_ALE GNDGND DVDDK GND GNDGND DVDDK GND IPERST WDT DI JTDO H TXD2 RxD3 EXD2 CTS3 N DVDD33 GND GND DVDoK GnD DVDDK GND OGND PCIE_TX PCIE_TX PCIE_CK PCIE_CK VDD1 GND RTS2 N RTS3 N CTS2 DVDD33 GND DVDDK GND DVDDK GN GND GNDGND GND PCIE_RX PCIE_RX AVDD12 K B_ USB_DI DD: AVDD33 IGNDGNDGND GND DVDDK GNDPCIE_CKPCIE_CK GND PCIE_ RX PCIE_ RX L SSUSB GND GND NDGND GND GND GND CBG_AV CBG_ AVGND GNDGND GND CBG_VR PCIE_ TX PCIE_TX L M SSUSB_TSSUSB-IGND USB_ D DVDD G DVDD G DVDD G USB DP E1_ VRE GND NDGNI E1|0 GND PCIE_CK PCIE_CK IGND GND PCIE_RX PCIE RX I M AVDD10 DVDD_KAVDD33 GND GND PCIE_ TX PCIE_TX AFE PO AFE P2 N DVDD K AVDD33 GND ND GNDGND AVDD10GND AVDD10 GND XPTLGPIO0/ _SCI I2C_SD GND GND XPTI YIXPTL-XP SW TX ESW D SW IX P-B_P VN_B_P IGND VN_A-PAVDD10GND AVDDIOGND 1 DVDD_K DVDD33 PCRST-RXD1 TXD1 GNDGND GE2 EX 13N R ESW TX ESW TX ESW TX lESW TX VP_C_PIVN-CPlvP APIVeAPIGND GNDGND GND DVDDK DVDD GA POR MDC GE2_RX GE2_RX GE2_RX SCL OBPS N SW TX ESW TX ESW TX UVP DPWN DP GND VN DVDD GI DVDD33 DVDD3 IDIO GE2_RX GE2_AX U 04 ESW TX ESW SW TA EsWⅪ ESW XO|GND DP IGND GND GND GE TX VP B P IVN B PGND GND CLK C_ CPIN BPAVSS3 EW人 TX ESW TX ESW TX ESW TX ESW TX SW TX ESW TX ESW VN BPIGND VN D P ESW P2 ESW_PO GE2_TX GE2_TX VBG LED 0 LED 1D1 SW TX ESW TX ESW TX TESW TX ESW TX ESW TX ESW TX ESW TX ESW TX ESW TX ESW TX ESW VP D PVP B VNCPIWN DPIN APIVN B P IVP CP VN A P VP B P VN C IVP D P ESW PA P1 GE2_TX GE2_TX LED_O_LED_O D3 SW TX ESW TX ESW TX ESW TX ESW TX ESW P3 AA GND A_A P GND GND VN C P IVP A P ESW PO VP C P ⊥LED_0 LED O GND 6 Table 2-1 Ball map DSMT7621 V.0.2 Prelimanary Page 6 of 43 Ralink MT7621 DATASHEET A MEDIATEK COMPANY 2.3 Pin Descriptions(TFBGA) Pin Name Type Dri Description GPIO P12 GPIOO O,IPU4 ma GPO0 (output only) UART R13 RXD1 L IPU 4 mA UART LIte RⅩData R14 TXD1 O. IPU 4 mA UART Lite TX data H4 RXD L IPD 4 mA UART RX Data H2 TXD2 O. IPD 4 mA UART TX Data CTS2 N L IPD 4 mA UART Clear To send J3 RTS2 N O. IPD 4 mA UART Request To Send H3 RXD3 L IPD 4 mA UART RX Data H1 TXD3 O. IPD 4 mA UART TX Data H5 CTS3 N ,IPD 4 mA UART Clear To Send 」4 RTS3 N O. IPD 4 mA UART Request To send JTAG G17 JTDO O,IPDA 4 mA JTAG Data Output G16 JTDI 10, IPD 4 mA JTAG Data Input G18 JTMS 1/0, IPD 4 mA TAG Mode Select F16 JTCLK yO,IPD4mA d-JTAG Clock F17 JTRST N 10, IPU 4 mATAG Target Reset 120 P13 12C SCLK 10, IPD 4 mA 12C Clock P14 12C SD O. IPD 4 mA 12C Data NAND ND CS N O. IPU 4 mA NAND Flash Chip select F3 ND RE N ○,|PU 4 mA NAND Flash read enable G4 ND WE N O IPU 4 mA NAND Flash Write Enable F4 ND WP 6 mA NAND Flash Write Protect ND CLE 000 6 mA NAND Flash Command Latch Enable G5 ND ALE 6 ma NAND Flash ALE Latch Enable F1 ND RB N 6 ma NAND Flash Ready/Busy F2 ND DO /O 6 mA NAND Flash datao E3 ND D1 6 mA NAND Flash data1 ND_D2 6 mA NAND Flash data2 E4 ND D3 1/0 6 mA NAND Flash data3 D1 ND D4 1/0, IPU 4 mA NAND Flash Data4 D2 ND D5 10, IPU 4 mA NAND Flash Data5 C1 nd D6 / O, IPU 4 mA NAND Flash Data6 D3 ND D7 10, IPU 4 ma NAND Flash Data7 RGMI/MIl (3.3 V) R17 GE2 RXCLK 12 mA RGMll2 R Clock T16 GE2 RXDV 12 a RGMll2 RX Data Valid DSMT7621 V.0.2 Prelimanary Page 7 of 43 Ralink MT7621 DATASHEET A MEDIATEK COMPANY Pil Name TypeD Description T17 GE2 RXDO 12 A RGMII2 Rx Data bit #O T18 GE2 RXD1 12 mA RGMll2 Rx Data bit #1 U16 GE2 RXD2 12 mA RGMII2 Rx Data bit#2 U17 GE2 RXD3 12 mA RGMII2 Rx Data bit #3 Ⅵ18 GE2 TXCLK 12mA|RGM1T×Cock V16 GE2 TXEN 12 mA RGMII2 Tx Data valid Ⅵ18 GE2 TXDO 12 mA RGMll2 Tx Data bit #o/ W17 GE2 TXD1 12 mA RGMIl2 TX Data bit #1 Y18 GE2 TXD2 12 mA RGMIl2 Tx Data bit #2 Y17 GE2 TXD3 12 ma RGMll2 Tx Data bit #3 PHY Management(3.3V) T15 MDC 6 ma PHY Management Clock. Shared with GPIO23 U15 MDIO 6 mA PHY Management Data. Shared with GPlO22 5-Port GiGa(10/100/1000)Switch AAl ESW PO LED O 1/0 Port #o PHY led indicators W16 ESW PO lEd 1 Port #o PHY LED indicators Y16 ESW P1 LED O Port #1 Phy led indicators W15 ESW P2 LED O Port #2 PHY LED indicators AA15 ESW P3 LED O 1/O Port #3 phY led indicators Y15 ESW P4 LED O Port #4 PhY LED indicators ESW REXT A Band gap resistor which is connected to W5 AVSS33 BG through a 24kQ2(+1%)resistor V5 ESW TANA A Analog test pin R5 ESW TXVNA PO A Port #o mdi transceivers R3 ESW_TXVNB PO A Port #o mdi transceivers T3 ESW TXVN C PO川A Port to mDi transceivers U2 ESW_TXVN_D_POA Port #o mDi Transceivers T5 ESW TXVP A PO A Port #o mDi transceivers R2 ESW TXVP B PO A Port #o mDi transceivers ESW TXVP C PO A Port #o mDi transceivers U1 ESW TXVP D PO A Port #o mDi transceivers U4 ESW TXVNAP1A Port #1 mDi transceivers V3 ESW TXVN B P1A Port #1 mDi Transceivers W2 ESW TXVN C P1A Port #1 mDi transceivers Y2 ESW TXVN D'P1A Port #1 MDi transceivers ESW TXVP A P1 Port #1 mDi transceivers V2 ESW TXVP B P1 A Port #1 mDi transceivers Ⅵ1 ESW⊥ TXVP C P1A Port #1 mdi transceivers Y1 ESW TXVP D P1 A Port #1 mDi Transceivers AA3 ESW TXVN A P2A Port #2 mDi transceivers W3 ESW_TXVN_B_P2A Port #2 mDi transceivers Y6 ESW TXVN_CP2 A Port #2 mDi transceivers DSMT7621 V.0.2 Prelimanary Page 8 of 43 Ralink MT7621 DATASHEET A MEDIATEK COMPANY Pil Name Type Driv. Description ESW TXVN D P2A Port #2 mDi Transceivers AA2 ESW TXVP A P2 A Port #2 MDI Transceivers ESW TXVP B P2 A Port #2 MDi transceivers W6 ESW TXVP C P2A Port #2 mDi transceivers W7 ESW-TXVPD_ P2A Port #2 MDI transceivers Y8 ESW TXVN A P3A Port #3 mdi transceivers Y9 ESW TXVN B P3 A Port t3 mDi transceivers AA10 ESW TXVN C P3A Port #3 mDi transceivers W10 ESW TXVN D P3A Port #3 mDi transceivers W8 ESW TXVP A P3A Port#3 mDi transceivers W9 ESW TXVP B P3 A Port #3 mDi transceivers Y10 ESW TXVP C P3 A Port #3 mdi transceivers V10 ESW TXVP D P3 A Port #3 mDi transceivers Y11 ESW TXVN A P4A Port #4 mDi transceivers W12 ESW TXVN B P4 Port #4 MDi transceivers Y13 ESW TXVNC P4A Port #4 mdi transceivers W14 ESW_TXVN_D_P4A Port #4 mdi transceivers AAl1 ESW TXVP A P4 A Port #4 mDi transceivers Y12 ESW TXVP B P4 A Port #4 mdi transceivers AA13 ESW TXVP CP4 A Port #4 mdi transceivers Y14 ESW TXVP DP4A Port #4 mdi transceivers Switch XTAL clock input (for debug) V8 ESW XO Switch XTAL clock input (for debug T12 A POR BPS Switch debug pin PCle G14 PERST N O,IPU ma PICe reset. H13 PCIE CKNO PCleO reference clock (negative) H14 PCIE CKPO PCleO reference clock(positive) H17 PCIE TXNO PCleo differential transmit tx H16 PCIE TXPO PCleo differential transmit tx+ J16 PcERⅩNo PCleo differential receive rx 」17 PCIE RXPO PCleo differential receive rx K14 PCIE CKN1 PClel reference clock (negative) K13 PCIE CKP1 PClel reference clock(positive) L17 PCIE TXNT 0000 PClel differential transmit ix L18 PCIE TXP 1 PCle1 differential transmit tx+ K16 PCIE RXN1 PCle1 differential receive rx K17 PCIE RXP1 PCle1 differential receive rx+ M14 PCIE CKN2 PCle2 reference clock(negative) M13 PCIE CKP2 N17 PCIE TXN2 0000 PCle2 reference clock (positive) PCle2 differential transmit tx N16 PCIE TXP2 PCle2 differential transmit tx+ DSMT7621 V.0.2 Prelimanary Page 9 of 43 Ralink MT7621 DATASHEET A MEDIATEK COMPANY Pil Name Type Driv. Description M18 PCIE RXN2 PCle2 differential receive rx M17 PCIE RXP2 PCle2 differential receive rx USB L2 SSUSB VRT 1/O USB Porto reterence pin(USB3.0) SSUSB RXN USB Porto ss data pin RX-(USB30 N2 SSUSB RXP USB Porto sS data pin rX+(USB3.0) M1 SSUSB TXN USB Porto ss data pin TX-(USB3 0 M2 SSUSB TXP 1/0 USB Porto SS data pin TX+(USB3.0) M4 USB DM PO USB Porto HS/FS/LS data pin Data-(USB3. 0) M5 USB DP PO USB PortO HS/ FS/LS data pin Data+(USB3 0 USb DM P1 USB Port1 data pin Data-(USB2.0) K2 USB DP P1 /O USB Port1 data pin Data+(USB2.0 DDR2/3 C11 RDQO 1/0 DDR Data bit #o B3 RDQl 1/0 DDR Data bit #1 A11 RDQ2 DDR Data bit #2 A2 RDQ3 DDR Data bit #3 B12 RDQ4 DDR Data bit #4 B2 RDQ5 1/O DDR Data bit #5 C12 RDQ6 DDR Data bit #6 RDQ7 DDR Data bit #7 A3 RDQ8 DDR Data bit #8 C10 RDQ9 1/0 DDR Data bit #9 B4 RDQ10 DDR Data bit #10 B10 RDQ11 1/0 DDR Data bit #11 A5 RDQ12 DDR Data bit #12 B9 RDQ13 1/O DDR Data bit #13 RDQ14 DDR Data bit #14 C8 RDQ15 DDR Data bit #015 E14 RAO DDR Address bit #o B18 RA1 DDR Address bit #t1 D14 RA2 DDR Address bit #2 A16 RA3 DDR Address bit #3 E15 RA4 DDR Address bit #4 B16 RA5 DDR Address bit #5 D17 RA6 DDR Address bit #6 E11 RAZ DDR Address bit #7 D16 RAS DDR Address bit #8 D13 RA9 0000000000000 DDR Address bit 9 E13 RA10 DDR Address bit #10 C18 RA11 DDR Address bit #11 D15 RA12 DDR Address bit #t12 DSMT7621 V.0.2 Prelimanary Page 10 of 43

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