MT7621 Datasheet

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MTK 路由器处理器芯片 MT7621规格书,双核880M MIPS1004Kc,自带5口10M/100M/1000以太网和一个RGMII接口。
Ralink MT7621 DATASHEET A MEDIATEK COMPANY Table of contents OVERVIEV∴∴ FEATURES 222 FUNCTIONAL BLOCK DIAGRAMmmoowmw. ORDERING INFORMATION 2 TABLE OF CONTENTS.mmm. mmm 1. MAIN FEATURES 2. PINS B。。。。。日。着,看;看。,着非音音,鲁自音看;看。自看看看,香自。看垂 鲁量看鲁。音看。量自看。。看自。量垂。··自。D。D鲁 2.1 TFBGA(11.7 X 13.6 MM)347 BALL PACKAGE DIAGRAM 35666 211 BALL MAP( TOP VIEW1…… 2.3 PIN DESCRIPTIONS (TFBGA)................... 2.4 PIN SHARING SCHEMES∴ 14 24.1GP0 O pin share scheme,……,,…, 14 2. 4. 2 UART pin share scheme 15 2. 4.3 RGMl/ pin share schemes 16 2. 4. 4 WDT RST MODE pin share scheme 16 2. 4.5 PERST_ N pin share scheme... 16 2. 4.6 MDC/MDIO pin share scheme: :::::::: 16 2.4.7 NAND/SDXC/SP/ pin share scheme 17 2.4.8 XMl/ PHY/MAC Pin Mapping 2.5 BOOTSTRAPPING PINS DESCRIPTION ………………………………… 3. MAXIMUM RATINGS AND OPERATING COND|TONS∴,,…,…22 3. 1 ABSOLUTE MAXIMUM RATINGS .. 22 3.2 MAXIMUM TEMPERATURES∴…… 22 3.3 OPERATING CONDITIONS 3.4 THERMAL CHARACTERISTICS...... 22 3. 5 STORAGE CONDITIONS 23 3.6 EXTERNAL XTAL SPECFICATION 3.7 DC ELECTRICAL CHARACTERISTICS(TBU) 3.8 AC ELECTRICAL CHARACTERISTICS 24 3.8. 1 DDR SDRAM Interface,y 3.8.2 RGM// Interface. 26 3.8. 3 Ml/ Interface(25 Mhz).... 27 384 RvMIl Interface( PHY Mode m∥ Timing)(25Mhz/…… 28 3.8. 5 SP/ Interface 3.8.6/S interface 30 3.8.7 PCM Interface 3.8.812 CInterface....,.,. 31 A 3.8. 9 SD/O interface 3.8. 10 NAND Flash Interface Samsung Compatibe/ Device) 3.8. 1 1 Power On sequence 36 3.9 PACKAGE PHYSICAL DIMENSIONS 37 3.9.1 TEBGA(11.7mmx13.6mm)387ba∥s.……, 更. 37 3.9.2 Package Diagram Key.……,,… ,37 393MT7621 V/A marking........... 38 DSMT7621 V.0.2 Prelimanary Page 3 of 43 Ralink MT7621 DATASHEET A MEDIATEK COMPANY 3.9. 4 Reflow profile guideline 39 4, ABBREVIATIONS 40 REVISION HISTORY DSMT7621 V.0.2 Prelimanary Page 4 of 43 Ralink MT7621 DATASHEET A MEDIATEK COMPANY i Main Features The following table covers the main features offered by the Mt7621A. Overall, the MT7621A supports the requirements of an high-level AP/router, and a number of interfaces together with a large maximum RAM capacit Features MT7621A CPU MIPS1004KC(880 MHz) I-Cache, D-Cache 32 KB. 32 KB L2 Cache 256KB HNAT/HQos HNAT 2 Gbps forwarding Memory DRAM Controller 16b DDR2 128 MB, 800 Mbps DDR3 256MB, 1200 Mbps NAND all page 12Byte(max 512M bit Large page kByte(max 8G bit SPI Flash B addr mode(max 128Mbit 4B addr mode(max 512Mbit SD SD-XC (class 10) PCle USB 3.0 USB 2.0 Switch Sp GSW RGMl(1) 12S PCM 2C SPDIE-T UART LIte JTAG Package TEBGA387-11.7 mm x13.6 mm Table 1-1 Main features DSMT7621 V.0.2 Prelimanary Page 5 of 43 Ralink MT7621 DATASHEET A MEDIATEK COMPANY 2 Pins 2.1 TFBGA (11.7 mm x 13.6 mm)347 Ball Package Diagram 2.1.1 Ball Map(Top View) 347 1?34567:10nn11nn1 A GND RDQ3 RDQ8 RDQ12 RDQSO GND RDQ2 RBA2 RWE RA3 RCKE GND B REXTDN RDQ5 RDQ1 RDQ10 RDQMO RDQS1_ RDQM1 RDQ13 RDQ11 GNDRDQ4 RA13 RODT RCS RA5 RBA1RA1 c ND_D6 RDQ7 GND RDQ14 GND RDQS1 RDQ15 RCLK RDQS RDQO RDQD GND RRAS RCAS RBA0 RA14 RA11c D ND_ D4ND_ D5 ND_ D7 GND GND DVDD_D DVDD_D CLK GND DDR3RS DVDD_D RA12 RA8 D E DVDD_D AVDD3 ND-D? ND_D1 ND-_D3 GND DEIO GND GND RAZ ND RA:0 RA4 MEMP TPME TN_ME E MPLL MPLL ND_RB-ND_DO ND RE ND WP GND GND DVDDK DVDDK GND GND DVDD D DVDD U AVSS33 DRIO LMEMP GND 0033 DRIO ND CLE ND WE ND_ALE GND GND DVDDK GND GND DVDDKGND 2X04ICLK TRST N JTDOJTMS H D3TXD2 RXD3 RXD2 CTS3 N GNI PCIE TX PCIE TX GND GNDDVDDK GND DVDDK GND AVDD12 GND RTS2 N RTS3 N CTS2_N DVDDS GND DVDDK GND DVDDK GN SSUSB GNDGND GND GND PCIE_RX PCIE_RX AVDD12 3E AVDDE3 GND PCIE_CK PCIE_CK GND D GND DVDDK GN GND PCIE_RX PCIE_RX K SSUSB GND GNDGNDGNDGNDGND GND CBG_AV CBG_AV OUTP o GND GND GND CBG VR PCIE TX PCIE TX L DVDD G M SSUS3--TSSUSB TGND/MD sB DP E1_VRE DVDD G DVDD G GND PCIE CK PCIE CK D D GND GND PCIE_RX I PCIE_ RX E1|0 SSUSB- SSUSB-GND GND AVDD10 AVDD10 DVDD K AVDD33 AFE P GND GND PCIE_TX PCIE_ TX N P GNDGND GNI AVDD10GND AFE.P3IGND VDD_K AvDD33/kSC\ I2C_SD GND GND / XPTLK7 /XPTL_X AVDDIO GND GND SW TX ESW TX ESW IX AVDDIU B-P VN B-PGND NA P GND DVDD PORSI RXD1 TXD1 GND GN GE∠HX R ESW_TX ESW_TX ESW TX ESW TX VP-CPINCPIVPAPIVAPGND GND GNDGNI DVDD_ DVDD GA_ POR GND MDC GE2_RX GE2_RXGE2_RY E2 OBPS N SW TX ESW TX ESW TX DVDD G DVDD33 DVDD3 U VP- D_P VN D-P GND VN_A-P 210 10_4_0_4GND MDIO GE2_X GE2_RX D2 0 ESW TX ESW ESW TA GEZ TX VP_B-P VN GN GNDESW XI ESW XOIGND VP D P IGND GND GND GND w vPCP VN CPVN BPAVSS33 ESW RE ESW TX ESW TX ESW IX ESW TX ESWTr SW TX ESW TX ESW VBG vP_ IVP D_P VP AP IVP B_ IVN DPIGND VN_BPGND VN D P ESW_P2 ESW_ PO GE2_TX GE2_TX LED 0_LED 1 D1 SWTX ESW TX ESW_ TX ESW TX ESW TX ESW TX ESW TX ESW TX ES Y VP D P VN D P IVP B P UN-CPIVN DPWN APIVN B PIVP CP VN A_ VN CPVP D P ESW PA IESW-P1 GE2_TX GE2-TXY 3 LEU U LED 0 ESW TX IESW TX ESW TX AA GND VP A P VN A P GND GND VN-C_P VP_A-P VP C P ESW P3 AA LED O ESW_POGND LED O :-:7::xT 13 1151617138 Tabe2-1Ba∥Mp DSMT7621 V.0.2 Prelimanary Page 6 of 43 Ralink MT7621 DATASHEET A MEDIATEK COMPANY 2.3 Pin Descriptions(TFBGA) Pin Name Type Driv Description GPIO P12 GPIOO O,IPU 4 mA GPOO(output only). UART 3 RXD1 L, IPU 4 mA UART Lite rX data R14 TXD1 O, IPU 4 mA UART Lite TX Data H4 RXD2 L IPD 4 mA UART RX Data H2 TXD2 O. IPD 4 mA UART TX Data CTS2 N L IPD 4 mA UART Clear To send J3 RTS2 N O, IPD 4 mA UART Request To Send H3 RXD3 L IPD 4 mA UART RX Data H1 TXD3 O, IPD 4 mA UART TX Data H5 CTS3 N IPD 4 mA UaRT Clear To send RTS3 N O, IPD 4mA UART Request To Send JTAG G17 JTDO O IPD 4 mA ITAG Data Output G16 JTDI y0,IPD 4 mA JTAG Data Input G18 JTMS 1/0, IPD4 mA AG Mode select F16 JTCLK 1/0, IPD 4 mA JTAG Clock F17 JTRST N 0, IPU 4 mA JTAG Target Reset 2C P13 I2C SCLK 1/0, IPD 4 mA 12C Clock P14 12C SD ○,|PD 4 mA 12C Data NAND ND CS N O. IPU 4 mA NAND Flash Chip Select F3 ND RE N O. IPU 4 mA NAND Flash read Enable ND WE N O IPU NAND Flash Write Enable F4 ND WP 6 mA NAND Flash Write Protect ND CLE 6 mA NAND Flash Command latch enable G5 ND ALE O 6 mA NAND Flash le latch enable ND RB N 6 mA NAND Flash Ready/ busy ND DO 6 ma NAND Flash DataO E3 ND D1 /O 6 mA NAND Flash data1 E2 ND D2 1O 6 mA NAND Flash Data2 E4 ND D3 1/0 6 mA NAND Flash data3 D1 ND D4 10, IPU A NAND Flash Data4 D2 ND D5 10, IPU 4 mA NAND Flash Data5 C1 ND D6 10, IPU 4 mA NANd Flash data6 D3 ND D7 10, IPU 4 mA NAND Flash Data7 RGMI/MI(3.3 V) GE2 RXCLK 12 mA RGMI2 RX Clo T16 GE2 RXDV 12 mA RGMll2 RX Data Valid DSMT7621 V.0.2 Prelimanary Page 7 of 43 Ralink MT7621 DATASHEET A MEDIATEK COMPANY Pin Name Type D Description T17 GE2 RXDO 12 mA RGMII2 RX Data bit #O T18 GE2 RXD1 12 mA RGMII2 Rx Data bit #1 U16 GE2 RXD2 12 mA RGMll2 Rx Data bit#2 U17 GE2 RXD3 12 mA RGMll2 Rx Data bit #3 V18 GE2 TXCLK /O 12 mA RGM112 Tx Clock V16 GE2 TXEN 12 mA RGMll2 Tx Data Valid W18 GE2 TXDO O000 12 mA RGMll2 Tx Data bit #O W17 GE2 XD1 12 mA RGMll2 TX Data bit #1 Y18 GE2 TXD2 12 mA RGMll2 Tx Data bit #2 Y17 GE2 TXD3 12 ma RGMll2 Tx Data bit#3 PHY Management(33Ⅵ) T15 MDC 6 mA PHY Management Clock. Shared with GPl023 U15 MDIO 6 ma PHY Management data. shared with gplo22 5-Port GiGa(10/100/1000 Switch AA17 ESW PO LED 0 70 Port #O PHY LED indicators W16 ESW PO LEd 1 Port #o PhY LED indicators Y16 ESW P1 LED O Port #1 PhY lEd indicators W15 ESW P2 LED O 10 Port #2 PHY LED indicators AA15 ESW P3 LED O Port #3 PhY LEd indicators Y15 ESW_P4_LED_0/O Port #4 phY led indicators ESW REXT A Band gap resistor which is connected to W5 AVSS33 BG through a 24k92(+1%)resistor V5 ESW TANA Analog test pin R5 ESW TXVN A PO A Port to mdi transceivers ESW TXVNB A Port #o mdi transceivers T3 ESW_TXVNC POA Port to mdi transceivers U2 ESW TXVN D POA Port to mdi transceivers T5 ESW_TXVP-A_PO A Port to mdi transceivers R2 EsWTⅩVPBP0 A Port #o mdi transceivers ESW TXVP C PO A Port #o mdi Transceivers U1 ESW_TXVP/A Port #o mdi transceivers U4 ESW TXVN A P1A Port #1 mdi transceivers V3 ESW TXVN B P1/A Port f1 mdi transceivers W2 ESW TXVN C P1 Port #1 mDi Transceivers Y2 ESW_TXVND_P1A Port #1 md transceivers ESW TXVP A P1 Port #1 mdi transceivers V2 ESW_TXVP_B_P1A Port #1 mdi transceivers W1 ESW⊥TXVP_C_P1A Port #1 mdi transceivers Y1 ESW TXVP D P1 Port #1 mdi transceivers AA3 ESW TXVN A P2A Port #2 mdi transceivers W3 ESW TXVN B P2 Port #2 mDi transceivers Y6 ESW TXVN P2A Port #2 MDi Transceivers DSMT7621 V.0.2 Prelimanary Page 8 of 43 Ralink MT7621 DATASHEET A MEDIATEK COMPANY Pin Name Type D Description ESW_TXVN_D_P2 A Port #2 mDi Transceivers AA2 ESW TXVP A P2 A Port #2 mdi Transceivers ESW TXVP B P2A Port #2 mDi Transceivers W6 ESW TXVP C P2 Port #2 mDi Transceivers W7 ESW TXVP D P2A Port #2 mDi transceivers Y8 ESW TXVN A P3 Port #3 mditransceivers Y9 ESW_TXVN_B_P3A Port #3 mdi transceivers AAl0 ESW TXVN C P3 Port #3 mdl Transceivers W10 ESW_TXVN_D_P3 A Port #3 mdi transceivers W8 ESW TXVP A P3A Port #3 MDI Transceivers W9 ESW TXVP B P3 A Port #3 mdi transceivers Y10 ESW TXVP C P3A Port t3 mdi transceivers V10 EsWTⅩvPDP3 A Port #3 mdi transceivers Y11 ESW TXVN A P4 A Port #4 mdi transceivers W12 ESW TXVN B P4 Port f4 MDi transceivers ESW TXVNC P4A Port #4 mdi transceivers ESW TXVND P4A Port #4 mdi transceivers AA11 ESW TXVP A P4A Port #4 mdi transceivers Y12 ESW TXVP B P4 A Port #4 mdi transceivers AA13 EsWTⅩVPCP4 A Port #4 mdi transceivers Y14 ESW TXVP D P4A Port #4 mdi transceivers V7 ESW XI Switch XTAL clock input(for debug V8 EsWⅩO Switch XTAL clock input for debug T12 A POR BPS Switch debug pin PCle G14 PERST N O. PU 4 mA PICe reset H13 PCIE CKNO PCleO reference clock(negative) 14 PCIE CKPO PCleO reference clock(positive) H17 PCIE TXNO O000 PCleo differential transmit tx H16 PCIE TXPO PCleo differential transmit tx+ 6 PCIE RXNO PCleo differential receive rx J17 PCIE RXPO PCleo differential receive rx+ K14 PCIE CKN1 PCle1 reference clock (negative) K13 PCIE CKP1 PClel reference clock(positive) L17 PCETⅩN1 PCle1 differential transmit tx L18 PCIE TXP1 PCle1 differential transmit Tx+ K16 PCIE RXN1 PCle1 differential receive rx K17 PCIE RXP1 PCle1 differential receive rx+ M14 PCIE CKN2 PCle2 reference clock(negative) M13 PCIE CKP2 PCle2 reference clock(positive) N17 PCIE TXN2 PCle2 differential transmit tx N16 PCIE TXP2 PCle2 differential transmit tx+ DSMT7621 V.0.2 Prelimanary Page 9 of 43 Ralink MT7621 DATASHEET A MEDIATEK COMPANY Pin Name Type D Description M18 PCIE RXN2 PCle2 differential receive rx M17 PCIE RXP2 PCle2 differential receive rx USB L2 SSUSB VRT USB Porto reference pin(USB3.0) n3 SSUSB RXN /O USB Porto ss data pin RX-(USB30 N2 SSUSB RXP USB Porto ss data pin RX+(USB3. 0) M1 SSUSB TXN USB Porto SS data pin TX(USB3.0) M2 SSUSB TXP 70 USB Porto S data pin TX+ (USB30 M4 USB DM PO 1/O USB Porto HS/FS/LS data pin Data-(USB3.0) M5 USB DP PO USB Porto HS/FS/LS data pin Data+(USB3.0) USB DM P1 /0 USB Port1 data pin Data-(USB2.0) K2 USB DP P1 /O USB Port1 data pin Data+(USB2.0) DDR2 /3 C11 RDQO O DDR Data bit #o B3 RDQl 70 DDR Data bⅰt#1 A11 RDQ2 DDR Data bit #2 A2 RDQ3 DDR Data bit #3 B12 RDQ4 10 DDR Data bit #4 B2 RDQ5 DDR Data bit #5 C12 RDQ6 DDR Data bit #6 RDQZ O DDR Data bit #7 A3 RDQ8 DDR Data bit #8 C10 RDQ9 1/0 DDR Data bit #9 B4 RDQ10 lO DDR Data bit #10 B10 RDQ11 DDR Data bit #11 A5 RDQ12 1/O DDR Data bit #12 B9 RDQ13 /0 DDR Data bit #13 RDQ14 DDR Data bit #14 C8 RDQ15 DDR Data bit #015 E14 RAO/ DDR Address bit #o B18 RA1 DDR Address bit #1 D14 RA2 O DDR Address bit #2 A16 RA3 DDR Address bit #3 E15 RA4 DDR Address bit #4 B16 RA5 DDR Address bit #5 D17 RA6 DDR Address bit #6 E11 RA了 DDR Address bit #7 D16 RA8 DDR Address bit #8 D13 RA9 DDR Address bit #9 E13 RA10 DDR Address bit #10 C18 RA11 DDR Address bit #11 D15 RA12 DDR Address bit #12 DSMT7621 V.0.2 Prelimanary Page 10 of 43

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