面向高效的VersatileVideoCoding(VVC)标准的实时软件解码器实现研究资源-CSDN文库

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TOWARDS A LIVE SOFTWARE DECODER IMPLEMENTATION

FOR THE UPCOMING VERSATILE VIDEO CODING (VVC) CODEC

Adam Wieckowski, Gabriel Hege, Christian Bartnik, Christian Lehmann, Christian Stoffers,

Benjamin Bross, and Detlev Marpe

Fraunhofer HHI, Video Coding & Analytics, Berlin, Germany

ABSTRACT

Versatile Video Coding (VVC) is the emerging video coding

standard to be finalized by the Joint Video Experts Team in

July 2020. Compared to its predecessor, the High Efficiency

Video Coding (HEVC) standard, VVC provides 50% bit-rate

reduction at comparable visual quality for natural video con-

tent in high-definition (HD) and ultra high-definition (UHD)

resolution. To achieve this, the standard incorporates more

advanced and generalized algorithms, leading to an increase

in computational complexity. This includes for example ad-

ditional in-loop filters, decoder-side motion refinement and

search as well as an increased number of transforms, which

creates a grand challenge for implementers to achieve live de-

coding on general-purpose CPUs.

In this paper, the work on an efficient software decoder

implementation for the upcoming VVC standard is described,

including optimization of sample operations using single in-

struction multiple data (SIMD) instructions and paralleliza-

tion approaches with multithreading. As a result, the pre-

sented decoder can perform live decoding of 10bit HD video

at 60 frames per second (fps) and 10bit UHD video at 30fps

on modern mobile consumer hardware, showcasing that VVC

live decoding is possible already right before finalization of

the standard.

Index Terms— VVC, software decoding, video coding,

SIMD, AVX2, multi-threading.

1. INTRODUCTION

VVC [1][2] is the emerging new video coding standard

jointly developed by the ITU-T Video Coding Experts Group

(VCEG) and the ISO/IEC Moving Pictures Experts Group

(MPEG), and to be finalized in July 2020. VVC provides 50%

bit-rate reduction over HEVC [3] standard and besides that,

VVC is designed to efficiently cope with even higher resolu-

tion, dynamic range and color gamut as well as with a variety

of different applications. This includes adaptive streaming

use cases with reference picture resampling and tem-

poral/spatial scalability, immersive applications using 360-

degree video, and screen-content coding for gaming and

screen sharing applications. The current state of standard de-

velopment is reflected in the specification draft text [1]. Ac-

companying the draft text is the VVC test model (VTM) [4],

which represents a reference software implementation of an

encoder and decoder. Its main focus is for experiments with

new technology and some coarse complexity analysis [5]. Be-

ing a reference implementation, it targets mainly correctness,

completeness and readability and thus, it is not supposed to

be used in production or consumer systems. For those reasons

the software is not properly optimized for performance. It

only has basic SIMD algorithm implementations, and does

not support any parallelization features on the decoder side.

As the comparison with the HEVC test model (HM) [4]

shows, the decoding complexity of the new standard is going

to be about twice that of HEVC [6]. Based on the times re-

ported in [4], for live play-back of UHD video content up to

40 Mbps, a decoder would on average need to be 30 times as

fast as the reference software, for HD content up to 20 Mbps,

7× speed-up is required. Some previous work is available on

VVC encoding complexity reduction [7-9], but to our

knowledge there is no current work on software decoder com-

plexity reduction.

In this paper, an optimized VVC software decoder im-

plementation is presented. As the standard is still under de-

velopment, the decoder is compatible with VVC draft 5 [1]

and VTM-5.2 with further integration and development work

ongoing, targeting compliance with the final standard shortly

after finalization in summer 2020.

2. VERSATILE VIDEO CODING COMPLEXITY

A schematic visualization of a VVC decoder pipeline is

shown in Fig. 1. It resembles the decoder schematics of an

CABAC iQ & iST & iT iLMCS

DBLF

SAO

ALF

Intra

LMCS

Inter

DPB

Input bitstream

Output video

Fig.

1: Schematic of a Versatile Video Coding decoder [

10][11].

New pipeline steps are marked cursive.

 

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