MIPS_Single_Cycle

在结构和行为VHDL中描述MIPS处理器的单周期（非流水线）版本，该版本支持以下MIPS ISA子集（即11条指令）： a) 7 Arithmetic/Logical instructions: add, sub, and, or, nor, slt, addi b) 2 Memory reference: lw, sw c) 2 Control transfer: beq, j 微体系结构的数据路径和控制路径如图1所示。您的内存地址转换/映射应遵循图2所示的约定。处理器具有以下接口： • Inputs - Clock (clk -> 1 bit) - Asynchronous reset for processor initialization and for mimicking program load (rst -> 1 bit) • In Vivado - Create a blank project - Add design and simulation source files - Run behavioral simulation - Your waveform configuration should be identical to the provided waveform snapshots, see Figure 3.