MIPS寄存器文件 (练习)

在行为VHDL中（使用3个并发进程）描述图1所示的MIPS寄存器文件，该文件通过以下接口支持3操作数算术运算： • Generics: - Register file size/depth (reg_file_depth with default value of 23 registers) - Register file width (reg_file_width with default value of 32 bits) • Inputs: - Clock (clk -> 1 bit) - Asynchronous reset (rst -> 1 bit) - Register write enable (RegWrite -> 1 bit) 1 -> enable writing to register file, 0 -> disable writing to register file - Read Address for first (read) operand (RA1 -> [log2 (reg_file_depth)] bits) - Read Address for second (read) operand (RA2 -> [log2 (reg_file_depth)] bits) - Write Address for third (write) operand (WA -> [log2 (reg_file_depth)] bits) - Write Data for third (write) operand (WD -> reg_file_width bits) • Outputs: - Read Data for first (read) operand (RD1 -> reg_file_width bits) - Read Data for second (read) operand (RD2 -> reg_file_width bits) • In Vivado - Create a blank project - Add design and simulation source files - Run behavioral simulation - Your waveform configuration should be identical to the provided waveform snapshot, see Figure 2. • In your design: - Guard against address-spilling (address-overflow) where addresses could go out of range, e.g., exceeding the register file size/depth. - Guard against unintentional writes to register zero ($0), i.e., $0 is read-only and has always the value 0.