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STM32，DMA

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June 2013 DocID13529 Rev 4 1/12

AN2548

Application note

Using the STM32F1x and STM32L1x DMA controller

Introduction

This application note describes how to use the STM32F1x and STM32L1x direct memory

access (DMA) controller. The STM32F1x and STM32L1x DMA controller, the Cortex™-M3

core, the advanced microcontroller bus architecture (AMBA) bus and the memory system

contribute to provide a high data bandwidth and to develop very-low latency response time

software.

This application note also describes how to take full advantage of these features and ensure

correct response times for different peripherals and subsystems.

The STM32F1x and STM32L1x will be referred to as STM32F1x/L1x, and the DMA

controller as DMA throughout the document.

Reference documents and firmware

• STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and STM32F107xx

advanced ARM-based 32-bit MCUs reference manual (RM0008)

• STM32F100xx advanced ARM-based 32-bit MCUs reference manual (RM0041)

• STM32L100xx, STM32L151xx, STM32L152xx and STM32L162xx advanced ARM-based

32-bit MCUs reference manual(RM0038)

• STM32F1x DMA firmware examples (STSW-STM32007)

• STM32F1x standard peripheral library (STSW-STM32054)

• STM32L1x standard peripheral library (STSW-STM32077)

Table 1. Application products and firmware

Type Part numbers and product categories

Microcontrollers

STM32F1 series

STM32L1 series

MCU software STSW-STM32007

www.st.com

DocID13529 Rev 4 3/12

AN2548 DMA controller description

1 DMA controller description

The DMA is an AMBA advanced high-performance bus (AHB) module that features two

AHB ports: a slave port for DMA programming and a master port that allows the DMA to

initiate data transfers between different slave modules.

The DMA allows data transfers to take place in the background, without the intervention of

the Cortex-M3 processor. During this operation, the main processor can execute other tasks

and it is only interrupted when a whole data block is available for processing. Large amounts

of data can be transferred with no major impact on the system performance.

The DMA is mainly used to implement central data buffer storage (usually in system SRAM)

for different peripheral modules. This solution is less expensive in terms of silicon and power

consumption compared to a distributed solution where each peripheral needs to implement

it own local data storage.

The STM32F1x/L1x DMA controller takes full advantage of the Cortex-M3 Harvard

architecture and the multilayer bus system in order to ensure very low latency both for DMA

transfers and for CPU execution/interrupt event detection/service.

Depending on the sales type used, one or two DMA controllers are implemented

1.1 Main features

The DMA(s) offer(s):

• Twelve DMA channels (7 for DMA1 and 5 for DMA2) supporting unidirectional data

transfers from source to destination

• Hardware- and software-programmable channel priority for each DMA

• Memory-to-memory, memory-to-peripheral, peripheral-to-memory and peripheral-to-

peripheral transfers (memory can be SRAM or Flash)

• Control of hardware/software transfers

• Automatic increment of peripheral and memory pointers

• Programmable data size

• Automatic bus-error management

• Non-circular/circular mode

• Transfer of up to 65536 data tokens

The DMA aims to offer a relatively large data buffer to all peripherals. This buffer is usually

located in system SRAM.

Each channel is assigned to a unique peripheral (data channel) at a given time. Peripherals

connected to the same DMA channel cannot be used simultaneously with active DMA (DMA

function active in the peripheral register).

To identify the different peripherals supporting DMA transfers for the STM32F1x and

STM32L1x product series, refer to direct memory access controller (DMA) section of the

corresponding reference manuals (RM0008, RM0041, and RM0038). These documents

contain the DMA block diagrams and the DMA request mapping from all the peripherals

connected to the DMA channels.

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