Verilog5分频

//------------even_division.v--------------//
module even_division(reset,clk,cout);
input clk,reset; 
output cout; 
reg[3:0] m,n;
wire cout;
reg cout1,cout2;
assign cout=cout1|cout2;
always @(posedge clk)
begin 
if(!reset)
begin 
cout1<=0;
m<=0;
end
else if(reset)
begin
if(m==4) 
begin 
m<=0;
end
else m<=m+1;
if(m==2) 
cout1=~cout1;
else if(m==4) 
cout1=~cout1;
end
end
always @(negedge clk)
begin