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GV7700.zip （2个子文件）

GV7700_Final_Data_Sheet_Rev8 (2).pdf 2.43MB

GV7700_RDK_User Guide_Rev2 (2).pdf 1.82MB

1 of 50

Semtech

GV7700

Final Data Sheet Rev.8

PDS-060377 March 2016

GV7700

HD-VLC™ Transmitter

www.semtech.com

Key Features

• Serial digital video transmitter for HD and 3G video

surveillance and HDcctv applications

• Quad rate operation: 270Mb/s, 540Mb/s, 1.485Gb/s,

and 2.97Gb/s

• Supports HDcctv 1.0, HD-SDI (ST 292), 3G-SDI (ST 424),

and SD-SDI (ST 259)

• Integrated High Definition Visually Lossless CODEC

(HD-VLC™) for extended cable reach:

 HD over 550m of Belden 543945 CCTV coax at

270Mb/s

 Full HD over 300m of Belden 543945 CCTV coax at

540Mb/s

 HD over 150m of Cat-5e/6 UTP cable at 270Mb/s

• Configurable 50/75Ω cable driver output, for both

coaxial and twisted pair cable transmission

• Integrated audio embedder with support for up to 4

channels of I

S serial digital audio at 32kHz, 44.1kHz

and 48kHz sample rates

• Downstream ancillary data insertion

• Supports both 720p and 1080p HD formats:

 Full HD: 1080p50/59.94/60fps

 HD: 1080p25/29.97/30fps

 HD: 720p25/29.97/30/50/59.94/60fps

• Support for both 8/10-bit and 16/20-bit BT.1120

compliant video interfaces, with embedded TRS or

external HVF timing

• 4-wire Gennum Serial Peripheral Interface (GSPI 2.0) for

external host command and control

• Dedicated JTAG test interface

• 1.8V core power supply and 1.8V or 3.3V digital I/O

supply

• Small-footprint 84-pin dual-row QFN (7mm x 7mm)

• Low power operation, typically 180mW

• Wide operating temperature range: -20°C to + 85°C

• Pb-free and RoHS compliant

Applications

• HD/3G security cameras

• Industrial cameras

• HD-SDI, 3G-SDI, and HDcctv peripherals

• Media converters

• Video multiplexers

Description

The GV7700 is a serial digital video transmitter for High

Definition component video. With integrated cable driving

technology, the GV7700 is capable of transmitting compressed

video at 270Mb/s or 540Mb/s, or uncompressed video at

1.485Gb/s or 2.97Gb/s, over 75Ω coaxial cable, or

differentially over 100Ω twisted pair cable.

The GV7700 integrates the High Definition Visually Lossless

CODEC (HD-VLC™) technology, which has been developed

specifically to reduce the transmission data rate of HD

video over both coaxial and unshielded twisted pair (UTP)

cable. This is achieved by encoding the HD video, normally

transmitted at a serial data rate of 1.485Gb/s, to the same

rate as Standard Definition (SD) video, at 270Mb/s serial

data rate.

550m Belden 543945

Coaxial Cable

GV7700

Transmitter

HD-VLC™ Camera

HD-VLC™ DVR

HD Video

CODEC

HDMI

Output

HD-SDI or

HD-VLC

Cameras

GV7704

Quad

Receiver

Image

Signal

Processor

HD Sensor

GV7700

Transmitter

Power

Sink

Power

Source

RS422RS422

IN1

IN2

IN3

IN4

150m Cat-5e/6 Cable

HD-VLC™ DVR

HD-VLC™

Camera

HDD

Storage

GV7704

Quad

Receiver

Coaxial Cable Application

UTP Cable Application

HD at 270Mb/s

GV7700

Final Data Sheet Rev.8

PDS-060377 March 2016

2 of 50

Semtech

www.semtech.com

At 270Mb/s, the effect of cable loss is greatly reduced,

resulting in much longer cable transmission. For 75Ω

coaxial cable, HD-VLC allows a 1.485Gb/s HD signal to be

transmitted up to 3x the normal reach. In typical video over

coaxial installations, when paired with Semtech’s GV7704

HD-VLC receiver, cable distances over 550m are possible.

Similarly, a 2.97Gb/s 3G signal can be transmitted at

540Mb/s using HD-VLC.

The GV7700 can also be configured to transmit HD and 3G

video over UTP cable, such as Cat-5e and Cat-6 cable, when

HD-VLC encoded at 270Mb/s and 540Mb/s, respectively.

The device supports both 8-bit and 10-bit per pixel YCbCr

4:2:2 BT.1120 component digital video. A configurable

20-bit or 10-bit wide parallel digital video input bus is

provided, with associated pixel clock and timing signal

inputs. The GV7700 supports direct interfacing of HD video

formats conforming to ITU-R BT.709 and BT.1120-6 for

1125-line formats, and SMPTE ST 296 for 750-line formats.

The GV7700 features an audio embedding core, which

supports up to 4 channels of I

S serial digital audio within

the ancillary data space of the video data stream. The audio

embedding core supports 32kHz, 44.1kHz, and 48kHz

sample rates.

The GV7700 supports the insertion of ancillary data into the

horizontal blanking of the video data stream. User data can

be programmed via the GSPI, allowing downstream

communication from the video source to sink device. The

ancillary data packing format is compliant with HDcctv 2.0

communications protocol.

Packaged in a space-saving 84-pin dual-row QFN, the

GV7700 is ideal for single PCB security cameras, where

high-density component placement is required. Typically

requiring only 180mW of power, the device does not

require any special heat sinking or air flow, reducing the

over-cost of HD security camera designs.

Frame structure with encoded HD only. Does not support

SD/D1 video.

Functional Block Diagram

GV7700 Functional Block Diagram

DIN_[19:0]

HIN

Formatter

GSPI

SDIN

SCLK

SDOUT

SDO

HD-VLC

Encoder

Audio

Ancilliary

Insertion

HDVLC

_EN

Digital Control

VIN

FIN

PCLK

Output

Formatter

BIT20_BIT10

DETECT_TRS

TRST

TDI

TMS

TCK

TDO

WCLK

ACLK

AIN

_1_2

AIN

_3_4

Test Pattern Generator

PLL

Tx Clock

XTAL

XTAL_OUT

Digital Clocks

P2S

RESET

AUDIO_EN

DIV_1001

XTAL54_SEL

SDO_50_EN

PCLK

RBIAS

JTAG Programming

XTAL_EN

XTAL

GV7700

Final Data Sheet Rev.8

PDS-060377 March 2016

3 of 50

Semtech

www.semtech.com

Revision History

Contents

1. Pin Out.................................................................................................................................................................5

1.1 GV7700 Pin Assignment ...................................................................................................................5

1.2 Pin Descriptions ..................................................................................................................................6

2. Electrical Characteristics............................................................................................................................. 10

2.1 Absolute Maximum Ratings ........................................................................................................ 10

2.2 DC Electrical Characteristics ........................................................................................................ 10

2.3 AC Electrical Characteristics ......................................................................................................... 11

3. Input/Output Circuits.................................................................................................................................. 13

4. Detailed Description.................................................................................................................................... 14

4.1 Functional Overview ...................................................................................................................... 14

4.2 Parallel Video Data Inputs DIN_[19:0] ......................................................................................15

4.2.1 Parallel Input In Video Mode........................................................................................... 15

4.3 Video Processing ............................................................................................................................. 21

4.3.1 H:V:F Timing .......................................................................................................................... 21

4.4 HD-VLC™ Encoder ............................................................................................................................ 22

4.5 Stream ID Packet Insertion ........................................................................................................... 24

4.6 Audio Embedding ........................................................................................................................... 25

Version ECO PCN Date Description

8 029991 — March 2016

Addition of Figure 3-3: XTAL_N, XTAL_P, XTAL_EN.

Updates to values in Table 4-6: Cable Reach for

Various Cable Types (In Meters).

7 029012 —

December

2015

Updated values in Table 2-3: AC Electrical

Characteristics.

6 028866 —

December

2015

Updated to Final Data Sheet from Preliminary Data

Sheet.

5 027517 —

September

2015

Removed Proprietary and Confidential from footer.

Updated Table 1-1, Table 2-3, Section 4.4,

Section 4.11, Section 4.14, Figure 4-18, and

Figure 6-1. Added Figure 6-2.

4 027026 — July 2015

Updated cable reach values. Updated Table 2-2

and Table 2-3.

3 025836 — May 2015

Updated to Preliminary Data Sheet from Draft Data

Sheet

2 025126 — April 2015

Updated GV7700 Functional Block Diagram,

Figure 1-1, Figure 6-1. Updated Table 2-2 and

Table 2-3. Various updates throughout document.

1 024223 — February 2015 Updated Table 1-1, Table 2-2, Section 4.1

0 020611 — August 2014 New Document

GV7700

Final Data Sheet Rev.8

PDS-060377 March 2016

4 of 50

Semtech

www.semtech.com

4.6.1 Serial Audio Data Inputs ................................................................................................... 25

4.6.2 Serial I2S Audio Data Format .......................................................................................... 26

4.6.3 Audio Mute............................................................................................................................ 26

4.6.4 ECC Error Detection and Correction............................................................................. 27

4.7 Ancillary Data Insertion ................................................................................................................. 27

4.8 Additional Processing Functions ............................................................................................... 29

4.8.1 Test Pattern Generation.................................................................................................... 29

4.8.2 TRS Generation and Insertion......................................................................................... 32

4.8.3 HD Line Number Calculation and Insertion............................................................... 32

4.8.4 Line Based CRC Generation and Insertion.................................................................. 32

4.8.5 Illegal Code Re-Mapping .................................................................................................. 32

4.9 Parallel to Serial Conversion ........................................................................................................ 32

4.10 PLL ...................................................................................................................................................... 33

4.10.1 Frequency Reference....................................................................................................... 33

4.11 Serial Data Output ........................................................................................................................ 34

4.11.1 Output Signal Interface Levels..................................................................................... 35

4.11.2 Serial Data Output Signal............................................................................................... 35

4.12 GSPI Host Interface ....................................................................................................................... 35

4.12.1 CS

Pin..................................................................................................................................... 35

4.12.2 SDIN Pin................................................................................................................................ 36

4.12.3 SDOUT Pin ........................................................................................................................... 36

4.12.4 SCLK Pin................................................................................................................................ 36

4.12.5 Command Word Description........................................................................................ 36

4.12.6 Data Word Description ................................................................................................... 37

4.12.7 GSPI Transaction Timing ................................................................................................ 38

4.12.8 Single Read/Write Access............................................................................................... 39

4.12.9 Auto-increment Read/Write Access........................................................................... 40

4.13 JTAG ................................................................................................................................................... 40

4.14 Power Supply and Reset Timing .............................................................................................. 41

5. Register Map................................................................................................................................................... 42

6. Typical Application Circuit ........................................................................................................................ 45

6.1 Power Supply Decoupling and Filtering ................................................................................. 46

7. Packaging Information ............................................................................................................................... 47

7.1 Package Dimensions ...................................................................................................................... 47

7.2 Recommended PCB Footprint .................................................................................................... 48

7.3 Marking Diagram ............................................................................................................................. 48

7.4 Solder Reflow Profile ...................................................................................................................... 49

7.5 Packaging Data ................................................................................................................................ 49

7.6 Ordering Information ..................................................................................................................... 49

GV7700

Final Data Sheet Rev.8

PDS-060377 March 2016

5 of 50

Semtech

www.semtech.com

1. Pin Out

1.1 GV7700 Pin Assignment

Figure 1-1: GV7700 Pin Out

RSVD

SDO_50_EN

DIN_19

DIN_17

DIN_15

DIN_14

DIN_12

DIN_10

DIN_8

DIN_7

DIN_5

DIN_4

DIN_3

DIN_2

DIN_0

FIN

HIN

VDDIO

VDDIO_XOUT

XTAL_OUT

VDD18_A

XTAL

VDD18_A

DIN_1

VDDIO

VIN

N/C

PCLK

N/C

CAP1

CAP2

CAP3

SDOUT

SCLK

SDIN

DIV_1001

WCLK

ACLK

AIN_3_4

XTAL54_SEL

VDDIO

DETECT_TRS

VDDIO

AUDIO_EN

AIN_1_2

HDVLC_EN

RSVD

TDO

TRST

TDI

VDDIO

CAP4

VDD18_A

VDDIO

TCK

TMS

RSVD

CAP5

VDD18_A

SDO

VDD18_A

RBIAS

RSVD

DIN_18

DIN_16

VDDIO

DIN_13

DIN_11

DIN_9

DIN_6

A10

A11

A12

A36

A35

A34

A33

A32

A31

A30

A29

A28

A27

A26

A25

B27

B26

B25

B24

B23

B22

B21

B20

B19

B10

B11

B12

B13

B14

B15

B16

B17

B18

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

B34

B33

B32

B31

B30

B29

B28

B36

B35

A48

A47

A46

A45

A44

A43

A42

A41

A40

A39

A38

A37

SDO

XTAL_EN

BIT20_BIT10

RESET

XTAL

VDDIO

THREEG_HD

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