MSP430x5xx Family
User's Guide
Literature Number: SLAU208
June 2008
Contents
Preface .............................................................................................................................. 15
1 System Resets, Interrupts, and Operating Modes, System Control Module (SYS) ............. 17
1.1 System Control Module Introduction .................................................................................... 18
1.2 Principle of Operation ...................................................................................................... 18
1.2.1 Device Descriptor Table .......................................................................................... 18
1.2.2 Boot Code .......................................................................................................... 18
1.2.3 Boot Strap Loader (BSL) ......................................................................................... 18
1.2.4 JTAG Mailbox System (JMB) .................................................................................... 19
1.3 Memory Map–Uses and Abilities ......................................................................................... 20
1.3.1 Vacant Memory Space ........................................................................................... 20
1.3.2 JTAG Lock Mechanism ........................................................................................... 20
1.3.3 SYS Interrupt Vector Generators ................................................................................ 21
1.4 Interrupts .................................................................................................................... 22
1.4.1 (Non)-Maskable Interrupts (NMI) ................................................................................ 22
1.4.2 SNMI Timing ....................................................................................................... 23
1.4.3 Maskable Interrupts ............................................................................................... 24
Interrupt Processing ............................................................................................... 24
1.5 Operating Modes ........................................................................................................... 26
1.5.1 Entering and Exiting Low-Power Modes ....................................................................... 28
1.6 Principles for Low-Power Applications .................................................................................. 30
1.7 Connection of Unused Pins ............................................................................................... 30
1.8 Reset and Subtypes ....................................................................................................... 30
1.9 Interrupt Vectors ............................................................................................................ 31
1.10 Special Function Registers ............................................................................................... 33
1.11 SYS Registers .............................................................................................................. 37
2 Watchdog Timer (WDT_A) ......................................................................................... 45
2.1 Watchdog Timer Introduction ............................................................................................. 46
2.2 Watchdog Timer Block Diagram.......................................................................................... 48
2.2.1 Watchdog Timer Counter......................................................................................... 48
2.2.2 Watchdog Mode ................................................................................................... 48
2.2.3 Interval Timer Mode ............................................................................................... 48
2.2.4 Watchdog Timer Interrupts ....................................................................................... 48
2.2.5 Clock Fail-Safe Feature .......................................................................................... 49
2.2.6 Operation in Low-Power Modes ................................................................................. 49
2.2.7 Software Examples ............................................................................................... 49
2.3 Watchdog Timer Registers ................................................................................................ 50
3 Unified Clock System (UCS) ....................................................................................... 53
3.1 Unified Clock System Introduction ....................................................................................... 54
3.2 Unified Clock System Module Operation ................................................................................ 56
3.2.1 Unified Clock System Module Features for Low-Power Applications ...................................... 56
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3.2.2 Internal Very-Low-Power Low-Frequency Oscillator (VLO) .................................................. 56
3.2.3 Internal Trimmed Low-Frequency Reference Oscillator(REFO) ............................................ 57
3.2.4 XT1 Oscillator ...................................................................................................... 57
3.2.5 XT2 Oscillator ...................................................................................................... 57
3.2.6 Digitally-Controlled Oscillator (DCO) ........................................................................... 58
3.2.7 Frequency Locked Loop (FLL) .................................................................................. 58
3.2.8 DCO Modulator .................................................................................................... 59
3.2.9 Disabling the FLL Hardware and Modulator ................................................................... 60
3.2.10 FLL Operation from Low-Power Modes ....................................................................... 60
3.2.11 Operation from Low-Power Modes, Requested by Peripheral Modules .................................. 60
3.2.12 Unified Clock System Module Fail-Safe Operation .......................................................... 61
3.2.13 Synchronization of Clock Signals .............................................................................. 64
3.3 MODOSC Module Oscillator .............................................................................................. 65
3.3.1 MODOSC Operation .............................................................................................. 65
3.4 Unified Clock System Module Registers ................................................................................ 66
4 Power Management Module and Supply Voltage Supervisor .......................................... 77
4.1 PMM Introduction ........................................................................................................... 78
4.2 PMM Operation ............................................................................................................. 80
4.2.1 Supply Voltage Supervisor and Monitor – High Side ......................................................... 82
4.2.2 Supply Voltage Supervisor and Monitor – Low Side ......................................................... 83
4.2.3 Supply Voltage Monitor Output (SVMOUT, Optional) ........................................................ 84
4.2.4 Performance Optimization........................................................................................ 84
4.2.5 Voltage Reference ................................................................................................ 85
4.2.6 Brown-Out Reset (BOR) .......................................................................................... 85
4.2.7 Manual Control of the Power Management Module .......................................................... 85
4.2.8 I/O-Port Control .................................................................................................... 86
4.2.9 PMM Interrupts .................................................................................................... 86
4.3 PMM Registers ............................................................................................................. 87
5 CPUX ...................................................................................................................... 95
5.1 CPU Introduction ........................................................................................................... 96
5.2 Interrupts .................................................................................................................... 98
5.3 CPU Registers .............................................................................................................. 99
5.3.1 Program Counter (PC) ............................................................................................ 99
5.3.2 Stack Pointer (SP) ............................................................................................... 100
5.3.3 Status Register (SR) ............................................................................................ 101
5.3.4 Constant Generator Registers (CG1 and CG2) ............................................................. 102
5.3.5 General Purpose Registers R4 to R15 ........................................................................ 103
5.4 Addressing Modes ........................................................................................................ 105
5.4.1 Register Mode .................................................................................................... 106
5.4.2 Indexed Mode .................................................................................................... 107
5.4.3 Symbolic Mode ................................................................................................... 111
5.4.4 Absolute Mode ................................................................................................... 116
5.4.5 Indirect Register Mode .......................................................................................... 118
5.4.6 Indirect, Autoincrement Mode .................................................................................. 119
5.4.7 Immediate Mode ................................................................................................. 120
5.5 MSP430 and MSP430X Instructions ................................................................................... 123
5.5.1 MSP430 Instructions ............................................................................................ 123
5.5.2 MSP430X Extended Instructions .............................................................................. 127
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5.6 Instruction Set Description ............................................................................................... 139
5.6.1 Extended Instruction Binary Descriptions..................................................................... 140
5.6.2 MPS430 Instructions ............................................................................................ 142
5.6.3 Extended Instructions ........................................................................................... 194
5.6.4 Address Instructions ............................................................................................. 235
6 Flash Memory Controller ......................................................................................... 251
6.1 Flash Memory Introduction .............................................................................................. 252
6.2 Flash Memory Segmentation ............................................................................................ 253
6.2.1 Segment A ........................................................................................................ 254
6.3 Flash Memory Operation ................................................................................................ 255
6.3.1 Erasing Flash Memory .......................................................................................... 255
6.3.2 Writing Flash Memory ........................................................................................... 259
6.3.3 Flash Memory Access During Write or Erase ................................................................ 266
6.3.4 Stopping Write or Erase Cycle ................................................................................. 267
6.3.5 Checking Flash memory ........................................................................................ 267
6.3.6 Configuring and Accessing the Flash Memory Controller .................................................. 267
6.3.7 Flash Memory Controller Interrupts ........................................................................... 267
6.3.8 Programming Flash Memory Devices ......................................................................... 267
6.4 Flash Memory Registers ................................................................................................. 269
7 Digital I/O ............................................................................................................... 273
7.1 Digital I/O Introduction ................................................................................................... 274
7.2 Digital I/O Operation ...................................................................................................... 275
7.2.1 Input Register PxIN .............................................................................................. 275
7.2.2 Output Registers PxOUT ....................................................................................... 275
7.2.3 Direction Registers PxDIR ...................................................................................... 275
7.2.4 Pullup/Pulldown Resistor Enable Registers PxREN ........................................................ 275
7.2.5 Output Drive Strength Registers PxDS ....................................................................... 276
7.2.6 Function Select Registers PxSEL ............................................................................. 276
7.2.7 P1 and P2 Interrupts ............................................................................................ 276
7.2.8 Configuring Unused Port Pins .................................................................................. 278
7.3 Digital I/O Registers ...................................................................................................... 279
8 RAM Controller ....................................................................................................... 285
8.1 RAMCTL Introduction .................................................................................................... 286
8.2 RAMCTL Operation....................................................................................................... 286
8.3 RAMCTL Module Registers ............................................................................................. 287
9 DMA Controller ....................................................................................................... 289
9.1 DMA Introduction ......................................................................................................... 290
9.2 DMA Operation ............................................................................................................ 292
9.2.1 DMA Addressing Modes ........................................................................................ 292
9.2.2 DMA Transfer Modes............................................................................................ 292
9.2.3 Initiating DMA Transfers ........................................................................................ 297
9.2.4 Stopping DMA Transfers ........................................................................................ 299
9.2.5 DMA Channel Priorities ......................................................................................... 299
9.2.6 DMA Transfer Cycle Time ...................................................................................... 300
9.2.7 Using DMA With System Interrupts ........................................................................... 300
9.2.8 DMA Controller Interrupts ....................................................................................... 300
9.2.9 Using the USCI_B I
2
C Module with the DMA Controller .................................................... 301
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