RapidIO_Bring-Up_Procedure_on_PowerQUICC

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Freescale Semiconductor

The MPC8540 and MPC8560 PowerQUICC III™ processors

have an 8-bit parallel RapidIO interface. This document provides

guidance in the basic use of this interface; detailing the setup of

local and remote processors starting with basic verification and

discovery, then describing booting over RapidIO and conducting

simple memory tests.

Most of the guidance in this document applies to any RapidIO

enabled PowerQUICC III system. However, the concepts are

illustrated by a few specific examples.

1 Introduction

This document is designed to provide assistance to engineers

wishing to use the RapidIO interface on the MPC8540 and

MPC8560 PowerQUICC III processors. It summarizes some basic

aspects of the RapidIO specification, and the use of the RapidIO

interfaces on these processors. It also details a basic procedure to

bring up simple RapidIO systems; including the setup of the local

processor, simplified discovery, booting over RapidIO, and the

execution of simple memory reads/writes to the remote

processors.

Section 2, “Background Information,” provides background

information regarding the RapidIO specifications, the

implementation and usage of the RapidIO interface on the

MPC8540/60, and information regarding the example systems,

which are used to illustrate the steps of the procedure outlined in

Section 3, “Bring-up Procedure.”

AN2753

Rev. 1, 11/2004

Contents

1.Introduction 1

1.1. Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

2.Background Information 3

2.1. RapidIO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

2.2. Using RapidIO on MPC8540 and MPC8560 . . . . . . .6

2.3. Example Target Hardware . . . . . . . . . . . . . . . . . . . . .8

3.Bring-up Procedure 11

3.1. Configure the Local Processor . . . . . . . . . . . . . . . . .12

3.2. Discover Other Devices in the System. . . . . . . . . . .20

3.3. Enable Access to Remote Configuration Space . . . .27

3.4. Boot over RapidIO . . . . . . . . . . . . . . . . . . . . . . . . . .30

3.5. Enable Memory Reads and Writes . . . . . . . . . . . . . .36

4.Output from Example Application 41

4.1. Point-to-Point Example. . . . . . . . . . . . . . . . . . . . . . .41

4.2. Fabric Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

5.References 54

6.Revision History 54

Appendix A. Notes on Maintenance Transactions . . . . . . .55

RapidIO Bring-Up Procedure on

PowerQUICC III™

by Lorraine McLuckie and Colin Cureton

NCSD Platforms, East Kilbride

RapidIO Bring-Up Procedure on PowerQUICC III™, Rev. 1

Freescale Semiconductor 3

Background Information

2 Background Information

This section provides background information relevant to the bring-up procedure. Section 2.1, “RapidIO,” provides

a summary of the relevant aspects of the RapidIO specification. Section 2.2, “Using RapidIO on MPC8540 and

MPC8560,” describes the implementation of RapidIO on MPC8540/60 and considerations for its use. Section 2.3,

“Example Target Hardware,” provides information regarding the example systems which will be used to illustrate

the procedure.

2.1 RapidIO

The RapidIO interconnect architecture is a high-performance packet-switched interconnect technology. It addresses

the high-performance embedded industry's need for reliability, increased bandwidth, and faster bus speeds in an

intra-system interconnect. The RapidIO interconnect allows chip-to-chip and board-to-board communications at

performance levels scaling to 10 Gigabits per second and beyond.

This section summarizes some basic information about the RapidIO specification. Additional information can be

found in the RapidIO Interconnect Specification.

2.1.1 RapidIO Layers

The RapidIO specification is written in a layered manner, to ensure flexibility and that changes to one layer do not

necessarily affect other layers.

The layers of the RapidIO architecture are as follows:

• Logical layer—Defines the overall protocol and packet formats, the types of transaction that can be carried

out with RapidIO and how addressing is handled.

• Transport layer—Provides the necessary route information for a packet to move from one point to another.

• Physical layer—Contains the device level interface such as packet transport mechanisms, flow control,

electrical characteristics, and low level error management.

The logical layer is split into two categories depending on the system model in use. The first part is the input/output

logical specification which defines the basic system architecture of RapidIO. The other is the message passing

logical specification which enables distributed I/O processing. This note concentrates on the input/output logical

specification.

2.1.2 Processing Element Models

There are several types of devices that can be used on a RapidIO based system. This note describes only two device

model types: the integrated processor-memory processing element and the switch processing element.

SDRAM Synchronous dynamic random access memory

TLB Translation lookaside buffer

Table 1. Glossary of Terms (continued)

Term Description

RapidIO Bring-Up Procedure on PowerQUICC III™, Rev. 1

4 Freescale Semiconductor

Background Information

2.1.2.1 Integrated Processor-Memory Processing Element

One form of the processor-memory processing element is a fully integrated component that is designed to connect

to a RapidIO interconnect system as shown in

Figure 1. This type of device integrates a memory system and other

support logic with a processor core on the same piece of silicon, or within the same package, and is one example of

a RapidIO end-point. In this note the processing element is an MPC8540/60 device.

Figure 1. Integrated Processor-Memory Processing Element

2.1.2.2 Switch Processing Element

A switch processing element is a device that allows communication with other processing elements through a

switch. A switch may be used to connect a variety of RapidIO compliant processing elements. Behavior of the

switches, and the interconnect fabric in general, is addressed in the RapidIO Common Transport Specification.

this note the switch processing element used is the Tundra Tsi500™ 4-port switch.

Figure 2. Switch Processing Element Model

2.1.2.3 RapidIO Transactions

In the logical layer, RapidIO defines a broad range of transaction types, ranging from simple transactions to access

an agent device’s memory space, to user defined and implementation dependent transactions. Throughout this note,

three different classes of request transactions and their associated responses are used, where a request is a transaction

that is issued by a processing element to accomplish some activity on a remote processing element. The three

transactions that are used in this note are detailed below. These sections detail the logical layer aspects of these

transaction; no consideration is given to the transport or physical layer interactions.

2.1.2.3.1 Maintenance Transaction

A maintenance transaction is a special system support request. It is used by a processing element to read or write

data to capability attribute registers (CARs) and capability status registers (CSRs), defined in the RapidIO

Processor

Memory

RapidIO Based

System Interconnect

Switch

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