1997 Jul 15 5
Philips Semiconductors Product specification
Clock/calendar with 240 × 8-bit RAM PCF8583
7 FUNCTIONAL DESCRIPTION
The PCF8583 contains a 256 by 8-bit RAM with an 8-bit
auto-increment address register, an on-chip 32.768 kHz
oscillator circuit, a frequency divider, a serial two-line
bidirectional I
2
C-bus interface and a power-on reset circuit.
The first 16 bytes of the RAM (memory addresses
00 to 0F) are designed as addressable 8-bit parallel
special function registers. The first register (memory
address 00) is used as a control/status register.
The memory addresses 01 to 07 are used as counters for
the clock function. The memory addresses 08 to 0F may
be programmed as alarm registers or used as free RAM
locations, when the alarm is disabled.
7.1 Counter function modes
When the control/status register is programmed, a
32.768 kHz clock mode, a 50 Hz clock mode or an
event-counter mode can be selected.
In the clock modes the hundredths of a second, seconds,
minutes, hours, date, month (four year calendar) and
weekday are stored in a BCD format. The timer register
stores up to 99 days. The event counter mode is used to
count pulses applied to the oscillator input (OSCO left
open-circuit). The event counter stores up to 6 digits of
data.
When one of the counters is read (memory locations
01 to 07), the contents of all counters are strobed into
capture latches at the beginning of a read cycle. Therefore,
faulty reading of the count during a carry condition is
prevented.
When a counter is written, other counters are not affected.
7.2 Alarm function modes
By setting the alarm enable bit of the control/status register
the alarm control register (address 08) is activated.
By setting the alarm control register a dated alarm, a daily
alarm, a weekday alarm or a timer alarm may be
programmed. In the clock modes, the timer register
(address 07) may be programmed to count hundredths of
a second, seconds, minutes, hours or days. Days are
counted when an alarm is not programmed.
Whenever an alarm event occurs the alarm flag of the
control/status register is set. A timer alarm event will set
the alarm flag and an overflow condition of the timer will set
the timer flag. The open drain interrupt output is switched
on (active LOW) when the alarm or timer flag is set
(enabled). The flags remain set until directly reset by a
write operation.
When the alarm is disabled (Bit 2 of control/status
register = 0) the alarm registers at addresses 08 to 0F
may be used as free RAM.
7.3 Control/status register
The control/status register is defined as the memory
location 00 with free access for reading and writing via the
I
2
C-bus. All functions and options are controlled by the
contents of the control/status register (see Fig.3).
7.4 Counter registers
In the clock modes 24 h or 12 h format can be selected by
setting the most significant bit of the hours counter
register. The format of the hours counter is shown in Fig.5.
The year and date are packed into memory location 05
(see Fig.6). The weekdays and months are packed into
memory location 06 (see Fig.7). When reading these
memory locations the year and weekdays are masked out
when the mask flag of the control/status register is set.
This allows the user to read the date and month count
directly.
In the event-counter mode events are stored in BCD
format. D5 is the most significant and D0 the least
significant digit. The divider is by-passed.
In the different modes the counter registers are
programmed and arranged as shown in Fig.4. Counter
cycles are listed in Table 1.
