dm3730 datasheet
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DM3730, DM3725
www.ti.com
SPRS685C–AUGUST 2010–REVISED JANUARY 2011
DM3730, DM3725
Digital Media Processors
Check for Samples: DM3730, DM3725
1 DM3730, DM3725 Digital Media Processors
1.1 Features
123456
• Load-Store Architecture With
• DM3730/25 Digital Media Processors:
Non-Aligned Support
– Compatible with OMAP™ 3 Architecture
• 64 32-Bit General-Purpose Registers
– ARM
®
Microprocessor (MPU) Subsystem
• Instruction Packing Reduces Code Size
• Up to 1-GHz ARM
®
Cortex™-A8 Core
• All Instructions Conditional
Also supports 300, 600, and 800-MHz
operation • Additional C64x+
TM
Enhancements
• NEON™ SIMD Coprocessor – Protected Mode Operation
– High Performance Image, Video, Audio – Expectations Support for Error
(IVA2.2
TM
) Accelerator Subsystem Detection and Program Redirection
• Up to 800-MHz TMS320C64x+
TM
DSP Core – Hardware Support for Modulo Loop
Also supports 260, 520, and 660-MHz Operation
operation
– C64x+
TM
L1/L2 Memory Architecture
• Enhanced Direct Memory Access (EDMA)
• 32K-Byte L1P Program RAM/Cache
Controller (128 Independent Channels)
(Direct Mapped)
• Video Hardware Accelerators
• 80K-Byte L1D Data RAM/Cache (2-Way
– POWERVR SGX™ Graphics Accelerator Set- Associative)
(DM3730 only)
• 64K-Byte L2 Unified Mapped RAM/Cache
• Tile Based Architecture Delivering up to (4- Way Set-Associative)
20 MPoly/sec
• 32K-Byte L2 Shared SRAM and 16K-Byte
• Universal Scalable Shader Engine: L2 ROM
Multi-threaded Engine Incorporating Pixel
– C64x+
TM
Instruction Set Features
and Vertex Shader Functionality
• Byte-Addressable (8-/16-/32-/64-Bit Data)
• Industry Standard API Support:
• 8-Bit Overflow Protection
OpenGLES 1.1 and 2.0, OpenVG1.0
• Bit-Field Extract, Set, Clear
• Fine Grained Task Switching, Load
• Normalization, Saturation, Bit-Counting
Balancing, and Power Management
• Compact 16-Bit Instructions
• Programmable High Quality Image
• Additional Instructions to Support
Anti-Aliasing
Complex Multiplies
– Advanced Very-Long-Instruction-Word
– External Memory Interfaces:
(VLIW) TMS320C64x+
TM
DSP Core
• SDRAM Controller (SDRC)
• Eight Highly Independent Functional
– 16, 32-bit Memory Controller With
Units
1G-Byte Total Address Space
• Six ALUs (32-/40-Bit); Each Supports
– Interfaces to Low-Power SDRAM
Single 32- bit, Dual 16-bit, or Quad 8-bit,
– SDRAM Memory Scheduler (SMS) and
Arithmetic per Clock Cycle
Rotation Engine
• Two Multipliers Support Four 16 x 16-Bit
• General Purpose Memory Controller
Multiplies (32-Bit Results) per Clock
(GPMC)
Cycle or Eight 8 x 8-Bit Multiplies (16-Bit
Results) per Clock Cycle
– 16-bit Wide Multiplexed Address/Data
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2POWERVR SGX is a trademark of Imagination Technologies Ltd.
3OMAP is a trademark of Texas Instruments.
4Cortex, NEON are trademarks of ARM Limited.
5ARM is a registered trademark of ARM Ltd.
6All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2010–2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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xuepiaojiangu2012-07-02英文版的，呵呵，与TI下载的一致。
u0147111372014-07-07与TI下载的一致
