library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clock is
port(clk:in std_logic;
clr:in std_logic;
en:in std_logic;
mode:in std_logic;
inc:in std_logic;
seg7:out std_logic_vector(6 downto 0);
scan:out std_logic_vector(5 downto 0));
end;
architecture one of clock is
signal state:std_logic_vector(1 downto 0);
signal qhh,qhl,qmh,qml,qsh,qsl:std_logic_vector(3 downto 0);
signal data:std_logic_vector(3 downto 0);
signal cnt:integer range 0 to 5;
signal clk1khz,clk1hz,clk2hz:std_logic;
signal blink:std_logic_vector(2 downto 0);
signal inc_reg:std_logic;
signal sec,min:integer range 0 to 59;
signal hour:integer range 0 to 23;
begin
process(clk)
variable count:integer range 0 to 9999;
begin
if clk'event and clk='1' then
if count=9999 then clk1khz<= not clk1khz;count:=0;
else count:=count+1;
end if;
end if;
end process;
process(clk1khz)
variable count:integer range 0 to 499;
begin
if clk1khz'event and clk1khz='1' then
if count =499 then clk1hz<=not clk1hz; count:=0;
else count:=count+1;
end if;
end if;
end process;
process(clk1khz)
variable count:integer range 0 to 249;
begin
if clk1khz'event and clk1khz='1' then
if count=249 then clk2hz<= not clk2hz;count:=0;
else count:=count+1;
end if;
end if;
end process;
process(mode,clr)
begin
if clr='1' then
state<="00";
elsif mode'event and mode='1' then
state<=state+1;
