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TC358746AXBG/TC358748XBG
Functional Specification
TOSHIBA
TC358746AXBG/748XBG Functional Specification Rev 0.9
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HISTORY
Revision
Date
Note
Rev 0.1
11/02/2012
Copy from tc358746 Rev 034 Spec
1. Change I2C slave address from 0x0000_111x to 0x0001_110x
2. Modify bit 0x0004[6] to turn on/off Parallel port properly with register
0x0032[15:14]
3. Remove PClk toggle requirement when RefClk is used
4. No need to toggle RefClk to get out of reset.
5. Update Revision ID to 0x01
Rev 0.2
03/18/2013
Add TC358748XBG for new package (section3.3,3.4.3.6)
Add Package ( 80 ball, 7.0 x 7.0 mm, 0.65 mm pitch) section7.2
Rev 0.3
04/21/2013
Corrected TC358748XBG ball assign
Rev 0.4
05/08/2013
Typo Correction
Rev 0.5
05/29/2013
Update Footer page
Rev 0.6
07/19/2013
1. Correct typo in Parallel In max PClk Freq to be 166 MHz
2. Add “Note” after Table 4-3 for packing muti-pixel/PClk possibility
Rev 0.7
08/13/2013
Remove 748 PinOut description, which should the same as those of 746A
Rev 0.8
11/18/2013
Update Fig 5-2 to indicate RefClk is required
Rev 0.9
03/28/2014
1. Remove Fail safe I2C pad operation
2. MClk can be output from GPIO0 in either mode
3. RefClk is not necessary, if not present/toggle, PClk/4 will be used to dirve
PLL
4. Change HSync/VSync to HValid/VValid
5. Update Fig. 5-2 and adding Fig 5-3 to indicate RefClk is Not required in
CSI-2 Tx mode
TC358746AXBG/748XBG Functional Specification Rev 0.9
TC358746A/748XBG Functional Spec Confidential Page 4 of 118
Copyright © 2005-2010 MIPI Alliance, Inc. All rights reserved.
MIPI Alliance Member Confidential.
All rights reserved. This material is reprinted with the permission of the MIPI Alliance, Inc. No part(s) of this document may be disclosed,
reproduced or used for any purpose other than as needed to support the use of the products of Toshiba Cooperation and its affiliates
REFERENCES
1. MIPI D-PHY, “MIPI_D-PHY_specification_v01-00-00, May 14, 2009"
2. MIPI CSI-2, "MIPI Alliance Standard for Camera Serial Interface 2 (CSI-2) Version 1.01
Revision Nov 2010"
3. I2C bus specification, version 2.1, January 2000, Philips Semiconductor
TC358746AXBG/748XBG Functional Specification Rev 0.9
TC358746A/748XBG Functional Spec Confidential Page 5 of 118
Copyright © 2005-2010 MIPI Alliance, Inc. All rights reserved.
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reproduced or used for any purpose other than as needed to support the use of the products of Toshiba Cooperation and its affiliates
Table of content
1 Overview ...................................................................................................................... 13
2 Features ....................................................................................................................... 15
2.1 Typical Power Consumption ................................................................................... 16
3 External Pins ................................................................................................................ 17
3.1 TC358746A pinout desctription ............................................................................... 17
3.2 TC358746AXBG BGA72 pin Count Summary ........................................................ 18
3.3 TC358748 BGA80 Pin Count Summary .................................................................. 18
3.4 TC358746A Pin Layout ........................................................................................... 19
3.5 TC358748 Pin Layout ............................................................................................. 20
3.6 System Overview .................................................................................................... 21
3.6.1 CSI-2 RX to Parallel Port Operation ........................................................................... 21
3.6.2 Parallel Port to CSI-2 TX Operation ............................................................................ 22
4 Function of Major Blocks ............................................................................................ 23
4.1 CSI-2 TX/RX Protocol ............................................................................................. 24
4.2 CSI-2 RX Interface Block ........................................................................................ 26
4.3 CSI-2 TX Interface Block ........................................................................................ 31
4.4 CSI-2 Packet Format .............................................................................................. 31
4.5 Checksum Generation ............................................................................................ 32
4.6 CSI-2 TX One Frame Operation ............................................................................. 32
4.6.1 Enable and Disable Parallel Input (Video) .................................................................. 33
4.7 Video Buffer Controller ............................................................................................ 34
4.8 Parallel Output mode .............................................................................................. 36
4.8.1 Overview ..................................................................................................................... 36
4.8.2 24-bit Un-Packed Data Format ................................................................................... 36
4.8.3 Timing Diagrams for Video signals (Vvalid and Hvalid) ............................................. 37
4.9 Parallel Input mode ................................................................................................. 38
4.9.1 Overview ..................................................................................................................... 38
4.9.2 Timing Diagrams for Video signals (Vvalid and Hvalid) ............................................. 39
4.10 I2C .......................................................................................................................... 39
4.10.1 Overview ..................................................................................................................... 39
4.10.2 I2C Write Access ......................................................................................................... 40
4.10.3 I2C Read Access ........................................................................................................ 40
4.11 SPI Slave Interface ................................................................................................. 41
4.11.1 Clocking Modes ........................................................................................................... 41
4.11.1.1 Timing Diagram ................................................................................................. 42
4.11.1.2 Providing Register Address over SPI Interface ................................................. 42
4.11.1.3 SPI Write Access Translation ............................................................................ 43
4.11.1.4 SPI Read Access Translation ............................................................................ 43
4.11.2 Full Duplex .................................................................................................................. 44
4.11.2.1 Back-2-back writes ............................................................................................ 45
4.11.2.2 Back-2-back reads ............................................................................................. 45
4.11.2.3 Write-after-Read ................................................................................................ 46
4.11.2.4 Read-after-Write ................................................................................................ 46
4.11.2.5 NOP-after-Read ................................................................................................. 47
5 Clock and System ........................................................................................................ 48
5.1 CG Block diagram ................................................................................................... 48
