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TC358748XBG/TC358746AXBG datasheet
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2019-04-19
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TC358748 XBG / TC358746 AXBG datasheet The MIPI® CSI-2 to Parallel port and Parallel port to CSI-2 (TC358746AXBG/TC358748XBG) is a bridge device that converts MIPI data transfers from devices such as a camera to an application processor over a Parallel port interface. All internal registers can be access through I2C or SPI (in CSI out case only).
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TC358746AXBG/TC358748XBG
1 / 19 2017-10-11
Rev.1.6a
© 2014-2017
Toshiba Electronic Devices & Storage Corporation
CMOS Digital Integrated Circuit Silicon Monolithic
TC358746AXBG/TC358748XBG
Mobile Peripheral Devices
Overview
The MIPI
®
CSI-2 to Parallel port and Parallel port to CSI-2
(TC358746AXBG/TC358748XBG) is a bridge device that converts
MIPI data transfers from devices such as a camera to an application
processor over a Parallel port interface. All internal registers can be
access through I
2
C or SPI (in CSI out case only).
Features
● CSI-2 TX/RX Interface
MIPI CSI-2 compliant (Version 1.01 Revision
0.04 – 2 April 2009)
Configurable to TX or RX controller
Supports up to 1Gbps per data lane
Supports up to 4 data lanes
Supports video data formats
- RX: RAW8/10/12/14, YUV422 (CCIR/ITU 8/10-
bit), RGB888/666/565 and User-Defined 8-bit
- TX: YUV422 (CCIR/ITU 8/10-bit), YUV444,
RGB888/666/565 and RAW8/10/12/14
● Parallel Port Interface
Supports data formats
- 24-bit bus – un-packed format (Both Input and
Output mode)
RGB888/666/565, RAW8/10/12/14 and
YUV422 8-bit (on 8/16-bit data bus) and 10-bit
data formats.
YUV444 (Parallel Input mode only)
- YUV422 8-bit – ITU BT.656 and ITU BT.601
(Parallel input mode only)
Up to 100 MHz PCLK frequency for Output
mode, and 166 MHz for Input mode.
● I
2
C Slave Interface (CS = L)
Support for normal (100 kHz), fast mode (400
kHz) and special mode (1 MHz)
Configure all TC358746AXBG/TC358748XBG
internal registers
● SPI Slave Interface (Only applicable in CSIOut
configuration, MSEL = H, and CS = H)
SPI interface support for up to 25 MHz
operation.
Configure all TC358746AXBG/TC358748XBG
internal registers
● GPIO signals
3 GPIO signals
- Three GPIO signals can be configured as
control signals (MCLK, CXRST, XShutdown) for
CSI-2 RX device.
- Or one GPIO signal can be configured as INT
signal for Parallel interface.
● System
Clock and power management support to
achieve low power states.
● Power supply inputs
Core and MIPI D-PHY: 1.2 V
I/O: 1.8 V – 3.3 V
P-VFBGA72-0404-0.40A3
Weight:
32 mg (Typ.)
Weight: 68 mg (Typ.)
P-VFBGA80-0707-0.65-001
TC358746AXBG
TC358748XBG
TC358746AXBG/TC358748XBG
2 / 19 2017-10-11
Table of content
REFERENCES ..................................................................................................................................................... 5
1. Overview .......................................................................................................................................................... 6
2. Features ........................................................................................................................................................... 8
2.1. Typical Power Consumption ...................................................................................................................... 9
3. External Pins .................................................................................................................................................. 10
3.1. TC358746AXBG pinout description ........................................................................................................ 10
3.2. TC358746AXBG BGA72 pin Count Summary ........................................................................................ 11
3.3. TC358748XBG BGA80 Pin Count Summary .......................................................................................... 11
3.4. TC358746AXBG Pin Layout .................................................................................................................... 12
3.5. TC358748XBG Pin Layout ...................................................................................................................... 13
4. Package ......................................................................................................................................................... 14
4.1. TC358746AXBG Package ....................................................................................................................... 14
4.2. TC358748XBG Package ......................................................................................................................... 15
5. Electrical Characteristics ................................................................................................................................ 16
5.1. Absolute Maximum Ratings ..................................................................................................................... 16
5.2. Operating Condition................................................................................................................................. 16
5.3. DC Electrical Specification ...................................................................................................................... 17
6. Revision History ............................................................................................................................................. 18
RESTRICTIONS ON PRODUCT USE ............................................................................................................... 19
Table of Figures
Figure 1.1 System Overview with TC358746AXBG/TC358748XBG in CSI-2 RX to Parallel Port
Configuration ......................................................................................................................................... 6
Figure 1.2 System Overview with TC358746AXBG/TC358748XBG in Parallel Port to CSI-2 TX
Configuration ......................................................................................................................................... 7
Figure 3.1 TC358746AXBG BGA72-Pin Layout (Top View) ................................................................... 12
Figure 3.2 TC358748XBG 80-Pin Layout (Top View).............................................................................. 13
Figure 4.1 TC358746AXBG P-VFBGA72-0404-0.40A3 package ........................................................... 14
Figure 4.2 TC358748XBG P-VFBGA80-0707-0.65-001 package ........................................................... 15
List of Tables
Table 3.1 TC358746AXBG/ TC358748XBG Functional Signal List ........................................................ 10
Table 3.2 TC358746AXBG BGA 72Pin Count Summary ........................................................................ 11
Table 3.3 TC358748XBG BGA 80 Pin Count Summary ......................................................................... 11
Table 4.1 TC358746AXBG P-VFBGA72-0404-0.40A3 Mechanical Dimension...................................... 14
Table 4.2 TC358748XBG P-VFBGA80-0707-0.65-001 Mechanical Dimension ..................................... 15
Table 6.1 Revision History ....................................................................................................................... 18
TC358746AXBG/TC358748XBG
3 / 19 2017-10-11
● MIPI and SLIMbus are registered trademarks of MIPI Alliance, Inc.
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