TLK1521原理资料

The data is then framed with a start and a stop bit, serialized and transmitted sequentially over the differential

high-speed I/O channel. The clock multiplier multiplies the reference clock (GTX_CLK) by a factor of 10 times

creating a bit clock. This internal bit clock is fed to the parallel-to-serial shift register, which transmits data on

both the rising and falling edges of the bit clock providing a serial data rate that is 20 times the reference clock.