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I/O扩展器
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TCA9555
SDA
I
2
C or SMBus Master
(e.g. Processor)
SCL
INT
V
CC
GND
A0
P00
P01
P02
P03
P04
P05
P06
P07
Peripheral
Devices
x RESET, EN or
Control Inputs
x INT or status
outputs
x LEDs
x Keypad
A1
A2
P10
P11
P12
P13
P14
P15
P16
P17
Product
Folder
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本文档旨在为方便起见,提供有关 TI 产品中文版本的信息,以确认产品的概要。 有关适用的官方英文版本的最新信息,请访问 www.ti.com,其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SCPS200
TCA9555
ZHCSJJ3E –JULY 2009–REVISED APRIL 2019
具具有有中中断断输输出出和和配配置置寄寄存存器器的的 TCA9555 低低电电压压 16 位位 I
2
C 和和 SMBus I/O
扩扩展展器器
1
1 特特性性
1
• 低待机电流消耗,最大为 3.5μA
• I
2
C 至并行端口扩展器
• 开漏电路低电平有效中断输出
• 可耐受 5V 电压的 I/O 端口
• 兼容大多数微控制器
• 400kHz 快速 I
2
C 总线
• 具有 3 个地址引脚的可配置从器件地址
• 极性反转寄存器
• 具有最大高电流驱动能力的锁存输出,可用于直接
驱动 LED
• 锁断性能超过 100mA,符合 JESD 78 II 类规范
• 静电放电 (ESD) 保护性能超过 JESD 22 规范的要
求
– 2000V 人体模型 (A114-A)
– 1000V 充电器件模型 (C101)
2 应应用用
• 服务器
• 路由器(电信交换设备)
• 个人计算机
• 个人电子产品
• 工业自动化设备
• 采用 GPIO 受限处理器的产品
3 说说明明
该面向两线双向总线 (I
2
C) 的 16 位 I/O 扩展器专为
1.65V 至 5.5V V
CC
工作电压而设计。它可通过 I
2
C 接
口为大多数微控制器系列产品提供通用远程 I/O 扩展。
TCA9555 由两个 8 位配置(输入或输出选择)、输入
端口、输出端口和极性反转(高电平有效或低电平有效
运行)寄存器组成。在加电时,I/O 被配置为输入。系
统主控制器可以通过写入 I/O 配置位将 I/O 启动为输入
或输出。每一个输入或者输出的数据被保存在相应的输
入或者输出寄存器内。输入端口寄存器的极性可借助极
性反转寄存器进行转换。
器器件件信信息息
(1)
器器件件型型号号 封封装装 封封装装尺尺寸寸((标标称称值值))
TCA9555
TSSOP (24) PW 7.80mm x 4.40mm
SSOP (24) DB 8.20mm x 5.30mm
WQFN (24) RTW 4.00mm x 4.00mm
VQFN (24) RGE 4.00mm x 4.00mm
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
简简化化原原理理图图
2
TCA9555
ZHCSJJ3E –JULY 2009–REVISED APRIL 2019
www.ti.com.cn
版权 © 2009–2019, Texas Instruments Incorporated
目目录录
1 特特性性.......................................................................... 1
2 应应用用.......................................................................... 1
3 说说明明.......................................................................... 1
4 修修订订历历史史记记录录 ........................................................... 2
5 说说明明 ((续续)).............................................................. 3
6 Pin Configuration and Functions......................... 4
7 Specifications......................................................... 5
7.1 Absolute Maximum Ratings ..................................... 5
7.2 ESD Ratings.............................................................. 5
7.3 Recommended Operating Conditions....................... 5
7.4 Thermal Information.................................................. 6
7.5 Electrical Characteristics........................................... 6
7.6 I
2
C Interface Timing Requirements.......................... 7
7.7 Switching Characteristics.......................................... 8
7.8 Typical Characteristics.............................................. 9
8 Parameter Measurement Information ................ 12
9 Detailed Description............................................ 15
9.1 Overview ................................................................. 15
9.2 Functional Block Diagram ....................................... 15
9.3 Feature Description................................................. 15
9.4 Device Functional Modes........................................ 16
9.5 Programming........................................................... 16
9.6 Register Maps......................................................... 24
10 Application and Implementation........................ 25
10.1 Application Information.......................................... 25
10.2 Typical Application ............................................... 25
11 Power Supply Recommendations ..................... 29
12 Layout................................................................... 31
12.1 Layout Guidelines ................................................. 31
12.2 Layout Example .................................................... 31
13 器器件件和和文文档档支支持持 ..................................................... 32
13.1 文档支持................................................................ 32
13.2 接收文档更新通知 ................................................. 32
13.3 社区资源................................................................ 32
13.4 商标 ....................................................................... 32
13.5 静电放电警告......................................................... 32
13.6 术语表 ................................................................... 32
14 机机械械、、封封装装和和可可订订购购信信息息....................................... 32
4 修修订订历历史史记记录录
注:之前版本的页码可能与当前版本有所不同。
Changes from Revision D (July 2016) to Revision E Page
• 更改了
器件信息
表 .................................................................................................................................................................. 1
• Changed the Pin Configuration images ................................................................................................................................. 4
Changes from Revision C (June 2016) to Revision D Page
• 已添加 向
器件信息
表中添加了 DB 封装................................................................................................................................. 1
Changes from Revision A (July 2009) to Revision B Page
• 已添加
添加了引脚配置和功能
部分、ESD
额定值
表、
特性 说明
部分、
器件功能模式
、
应用和实施
部分、
电源建议
部分、
布局
部分、
器件和文档支持
部分以及
机械、封装和可订购信息
部分 ......................................................................... 1
Changes from Revision B (July 2015) to Revision C Page
• 已添加 向
器件信息
表中添加了 RGE 封装.............................................................................................................................. 1
• Changed V
IH
for I
2
C pins limited to V
CC
, with note allowing higher voltage .......................................................................... 5
• Added I
OL
for different T
j
........................................................................................................................................................ 5
• Removed ΔI
CC
spec from the Electrical Characteristics table, added ΔI
CC
typical characteristics graph .............................. 6
• Changed I
CC
standby into different input states...................................................................................................................... 7
• Changed C
io
maximum .......................................................................................................................................................... 7
• Changed Typical characteristic plots with updated data ........................................................................................................ 9
• POR requirements, bounded lowest voltage allowed during glitch ..................................................................................... 30
3
TCA9555
www.ti.com.cn
ZHCSJJ3E –JULY 2009–REVISED APRIL 2019
Copyright © 2009–2019, Texas Instruments Incorporated
5 说说明明 ((续续))
除了包含内部 I/O 上拉电阻器之外,TCA9555 与 TCA9535 相同,该电阻器在配置为输入和未驱动时,可将 I/O 拉
至默认高电平。
三个硬件引脚(A0、A1 和 A2)用于对 I
2
C 地址进行编程,该地址允许高达八个 TCA9555 器件共享同一个 I
2
C 总
线或 SMBus。TCA9555 的固定 I
2
C 地址与 PCF8575、PCF8575C 和 PCF8574 相同,最多允许这些器件中任意
八个共享同一个 I
2
C 总线或 SMBus。
1INT 24
V
CC
2A1 23 SDA
3A2 22 SCL
4P00 21 A0
5P01 20 P17
6P02 19 P16
7P03 18 P15
8P04 17 P14
9P05 16 P13
10P06 15 P12
11P07 14 P11
12GND 13 P10
Not to scale
24 A27P06
1P00 18 A0
23 A18P07
2P01 17 P17
22 INT9GND
3P02 16 P16
21
V
CC
10P10
4P03 15 P15
20 SDA11P11
5P04 14 P14
19 SCL12P12
6P05 13 P13
Not to scale
Thermal
Pad
4
TCA9555
ZHCSJJ3E –JULY 2009–REVISED APRIL 2019
www.ti.com.cn
Copyright © 2009–2019, Texas Instruments Incorporated
6 Pin Configuration and Functions
DB, PW Package
24-Pin TSSOP
Top View
RTW, RGE Package
24-Pin WQFN, VQFN with Exposed Thermal Pad
Top View
The exposed thermal pad, if used, must be
connected as a secondary ground or left
electrically open.
Pin Functions
PIN
TYPE DESCRIPTION
NAME
NO.
DB, PW
RTW,
RGE
A0 21 18 Input Address input 0. Connect directly to V
CC
or ground
A1 2 23 Input Address input 1. Connect directly to V
CC
or ground
A2 3 24 Input Address input 2. Connect directly to V
CC
or ground
GND 12 9 GND Ground
INT 1 22 Output Interrupt output. Connect to V
CC
through a pull-up resistor
P00 4 1 I/O P-port I/O. Push-pull design structure. At power on, P00 is configured as an input
P01 5 2 I/O P-port I/O. Push-pull design structure. At power on, P01 is configured as an input
P02 6 3 I/O P-port I/O. Push-pull design structure. At power on, P02 is configured as an input
P03 7 4 I/O P-port I/O. Push-pull design structure. At power on, P03 is configured as an input
P04 8 5 I/O P-port I/O. Push-pull design structure. At power on, P04 is configured as an input
P05 9 6 I/O P-port I/O. Push-pull design structure. At power on, P05 is configured as an input
P06 10 7 I/O P-port I/O. Push-pull design structure. At power on, P06 is configured as an input
P07 11 8 I/O P-port I/O. Push-pull design structure. At power on, P07 is configured as an input
P10 13 10 I/O P-port I/O. Push-pull design structure. At power on, P10 is configured as an input
P11 14 11 I/O P-port I/O. Push-pull design structure. At power on, P11 is configured as an input
P12 15 12 I/O P-port I/O. Push-pull design structure. At power on, P12 is configured as an input
P13 16 13 I/O P-port I/O. Push-pull design structure. At power on, P13 is configured as an input
P14 17 14 I/O P-port I/O. Push-pull design structure. At power on, P14 is configured as an input
P15 18 15 I/O P-port I/O. Push-pull design structure. At power on, P15 is configured as an input
P16 19 16 I/O P-port I/O. Push-pull design structure. At power on, P16 is configured as an input
P17 20 17 I/O P-port I/O. Push-pull design structure. At power on, P17 is configured as an input
SCL 22 19 Input Serial clock bus. Connect to V
CC
through a pull-up resistor
SDA 23 20 Input Serial data bus. Connect to V
CC
through a pull-up resistor
V
CC
24 21 Supply Supply voltage
5
TCA9555
www.ti.com.cn
ZHCSJJ3E –JULY 2009–REVISED APRIL 2019
Copyright © 2009–2019, Texas Instruments Incorporated
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN MAX UNIT
V
CC
Supply voltage –0.5 6 V
V
I
Input voltage
(2)
–0.5 6 V
V
O
Output voltage
(2)
–0.5 6 V
I
IK
Input clamp current V
I
< 0 –20 mA
I
OK
Output clamp current V
O
< 0 –20 mA
I
IOK
Input-output clamp current V
O
< 0 or V
O
> V
CC
±20 mA
I
OL
Continuous output low current V
O
= 0 to V
CC
50 mA
I
OH
Continuous output high current V
O
= 0 to V
CC
–50 mA
I
CC
Continuous current through GND –250
mA
Continuous current through V
CC
160
T
j(MAX)
Maximum junction temperature 100 °C
T
stg
Storage temperature –65 150 °C
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.2 ESD Ratings
VALUE UNIT
V
(ESD)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
±2000
V
Charged-device model (CDM), per JEDEC specification JESD22-C101
or ANSI/ESDA/JEDEC JS-002
(2)
±1000
(1) For voltages applied above V
CC
, an increase in I
CC
results.
(2) The values shown apply to specific junction temperatures, which depend on the R
θJA
of the package used. See the Calculating Junction
Temperature and Power Dissipation section on how to calculate the junction temperature.
7.3 Recommended Operating Conditions
MIN MAX UNIT
V
CC
Supply voltage 1.65 5.5 V
V
IH
High-level input voltage
SCL, SDA 0.7 × V
CC
V
CC
(1)
V
A2–A0, P07–P00, P17–P10 0.7 × V
CC
5.5
V
IL
Low-level input voltage
SCL, SDA –0.5 0.3 × V
CC
V
A2–A0, P07–P00, P17–P10 –0.5 0.3 × V
CC
I
OH
High-level output current P07–P00, P17–P10 –10 mA
I
OL
Low-level output current
(2)
P07–P00, P17–P10
T
j
≤ 65°C 25
mAT
j
≤ 85°C 18
T
j
≤ 100°C 11
I
OL
Low-level output current
(2)
INT, SDA
T
j
≤ 85°C 6
mA
T
j
≤ 100°C 3.5
T
A
Operating free-air temperature –40 85 °C
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