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TI-SN74LS221是一款由德州仪器（TI）生产的双稳态多谐振荡器集成电路。这款芯片的设计特点在于其性能几乎与SN54121和SN74121单稳态触发器一致，同时具有相同的引脚配置，与SN54123、SN74123、SN54LS123和SN74LS123的引脚布局相同，便于在设计电路时进行替换。该芯片提供了两种版本：SN54221和SN74221。这两个版本的电气特性和开关特性几乎完全相同，都具备负边沿触发输入和正边沿触发输入，且任一输入可作为抑制输入。这意味着它们可以在相同的触发条件下产生稳定的脉冲输出。 SN54221和SN74221的最大输出脉冲长度不同，SN54221的最长输出脉冲为21秒，而SN74221的最长输出脉冲为28秒。对于SN54LS221和SN74LS221，其最大输出脉冲长度分别是49秒和70秒。这种差异主要源于不同系列在工作电压、功耗以及温度范围上的微小差别。在封装方面，TI-SN74LS221提供多种选择，包括PDIP（塑料双列直插式封装）、SOIC（小外形集成电路封装）、SOP（小外形封装）以及SSOP（薄型小外形封装）。此外，还有适用于极端温度范围的J封装和FK封装。每种封装都有对应的订单型号，例如PDIP封装的N系列芯片标记为SN74LS221N，而DIP封装的J系列芯片则标记为SNJ54LS221J。在应用中，SN74LS221常用于需要精确控制时序信号的场合，例如定时器、脉冲发生器或信号整形电路。每个独立的多谐振荡器单元（Q1和Q2）都可以单独控制，通过外部电容Cext和电阻Rext/Cext可以设置脉冲宽度。同时，通过CLR输入可以强制终止输出脉冲，实现对输出的即时复位。总体来说，TI-SN74LS221是一款高度稳定、灵活且兼容性强的双稳态多谐振荡器，适用于各种需要精确时序控制的电子系统设计。其详细的技术参数、封装信息、电气特性以及PCB设计指南等资料可在德州仪器的官方网站上找到。

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SDLS213B − DECEMBER 1983 − REVISED NOVEMBER 2004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Dual Versions of Highly Stable SN54121

and SN74121 One Shots

D SN54221 and SN74221 Demonstrate

Electrical and Switching Characteristics

That Are Virtually Identical to the SN54121

and SN74121 One Shots

D Pinout Is Identical to the SN54123,

SN74123, SN54LS123, and SN74LS123

D Overriding Clear Terminates Output Pulse

TYPE

MAXIMUM

OUTPUT

PULSE

LENGTH(S)

SN54221 21

SN74221 28

SN54LS221 49

SN74LS221 70

description/ordering information

The ’221 and ’LS221 devices are dual

multivibrators with performance characteristics

virtually identical to those of the ’121 devices.

Each multivibrator features a negative-transition-

triggered input and a positive-transition-triggered

input, either of which can be used as an inhibit

input.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP − N

Tube

SN74221N SN74221N

PDIP − N Tube

SN74LS221N SN74LS221N

0°C to 70°C

SOIC − D

Tube SN74LS221D

LS221

0°C to 70°C SOIC − D

Tape and reel SN74LS221DR

LS221

SOP − NS Tape and reel SN74LS221NSR 74LS221

SSOP − DB Tape and reel SN74LS221DBR LS221

CDIP − J

Tube

SNJ54221J SNJ54221J

−55°C to 125°C

CDIP − J Tube

SNJ54LS221J SNJ54LS221J

−55 C to 125 C

LCCC − FK Tube SNJ54LS221FK SNJ54LS221FK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

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3212019

10 11 12 13

ext

2CLR

1CLR

ext

GND

1CLR

ext

GND

ext

2CLR

SN54221, SN54LS221 ...J PACKAGE

SN74221 ...N PACKAGE

SN74LS221 . . . D, DB, N, OR NS PACKAGE

(TOP VIEW)

SN54LS221 . . . FK PACKAGE

(TOP VIEW)

ext

2R /C

ext

NC − No internal connection

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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SDLS213B − DECEMBER 1983 − REVISED NOVEMBER 2004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description/ordering information (continued)

Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input

pulse. Schmitt-trigger input circuitry (TTL hysteresis) for B input allows jitter-free triggering from inputs with

transition at rates as slow as 1 V/s, providing the circuit with excellent noise immunity, typically of 1.2 V. A high

immunity to V

noise, typically of 1.5 V, also is provided by internal latching circuitry.

Once fired, the outputs are independent of further transitions of the A and B inputs and are a function of the timing

components, or the output pulses can be terminated by the overriding clear. Input pulses can be of any duration

relative to the output pulse. Output pulse length can be varied from 35 ns to the maximum by choosing

appropriate timing components. With R

ext

= 2 kΩ and C

ext

= 0, an output pulse typically of 30 ns is achieved

that can be used as a dc-triggered reset signal. Output rise and fall times are TTL compatible and independent

of pulse length. Typical triggering and clearing sequences are shown as a part of the switching characteristics

waveforms.

Pulse-width stability is achieved through internal compensation and is virtually independent of V

and

temperature. In most applications, pulse stability is limited only by the accuracy of external timing components.

Jitter-free operation is maintained over the full temperature and V

ranges for more than six decades of timing

capacitance (10 pF to 10 µF) and more than one decade of timing resistance (2 kΩ to 30 kΩ for the SN54221,

2 kΩ to 40 kΩ for the SN74221, 2 kΩ to 70 kΩ for the SN54LS221, and 2 kΩ to 100 kΩ for the SN74LS221).

Throughout these ranges, pulse width is defined by the relationship: t

(out) = C

ext

In2 ≈ 0.7 C

ext

. In

circuits where pulse cutoff is not critical, timing capacitance up to 1000 µF and timing resistance as low as 1.4 kΩ

can be used. Also, the range of jitter-free output pulse widths is extended if V

is held to 5 V and free-air

temperature is 25°C. Duty cycles as high as 90% are achieved when using maximum recommended R

. Higher

duty cycles are available if a certain amount of pulse-width jitter is allowed.

The variance in output pulse width from device to device typically is less than ±0.5% for given external timing

components. An example of this distribution for the ’221 is shown in Figure 3. Variations in output pulse width

versus supply voltage and temperature for the ’221 are shown in Figures 4 and 5, respectively.

Pin assignments for these devices are identical to those of the SN54123/SN74123 or SN54LS123/SN74LS123

so that the ’221 or ’LS221 devices can be substituted for those products in systems not using the retrigger by

merely changing the value of R

ext

and/or C

ext

; however, the polarity of the capacitor must be changed.

FUNCTION TABLE

(each monostable multivibrator)

INPUTS

OUTPUTS

CLR A B Q Q

L X X L H

X HXLH

X XLLH

H L ↑

†

H ↓ H

†

↑

‡

L H

† †

†

Pulsed-output patterns are tested during

AC switching at 25°C with R

ext

= 2 kΩ, and

ext

= 80 pF.

‡

This condition is true only if the output of

the latch formed by the two NAND gates

has been conditioned to the logic 1 state

prior to CLR

going high. This latch is

conditioned by taking either A high or

B low while CLR

is inactive (high).

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SDLS213B − DECEMBER 1983 − REVISED NOVEMBER 2004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range, V

7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V

(see Note 1): ’LS221 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

’221 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θ

(see Note 2): D package 73°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DB package 82°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

N package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NS package 64°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

−65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions (see Note 3)

SN54221 SN74221

UNIT

MIN NOM MAX MIN NOM MAX

UNIT

Supply voltage 4.5 5 5.5 4.75 5 5.25 V

High-level output current −800 −800 µA

Low-level output current 16 16 mA

∆v/∆t

Rise or fall of input pulse rate

B input 1* 1 V/s

∆v/∆t Rise or fall of input pulse rate

A input

1* 1 V/µs

Operating free-air temperature −55 125 0 70 °C

∗ On products compliant to MIL-PRF-38535, this parameter is not production tested.

NOTE 3: All unused inputs of the device must be held at V

or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

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