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Preface
The simplest method of transferring data through the inputs or outputs of a
silicon chip is to directly connect each bit of the datapath from one chip to the
next chip. Once upon a time this was an acceptable approach. However, one
aspect (and perhaps the only aspect) of chip design which has not changed
during the career of the authors is Moore’s Law, which has dictated substantial
increases in the number of circuits that can be manufactured on a chip. The pin
densities of chip packaging technologies have not increased at the same pace
as has silicon density, and this has led to a prevalence of High Speed Serdes
(HSS) devices as an inherent part of almost any chip design.
HSS devices are the dominant form of input/output for many (if not most)
high-integration chips, moving serial data between chips at speeds up to 10
Gbps and beyond. Chip designers with a background in digital logic design
tend to view HSS devices as simply complex digital input/output cells. This
view ignores the complexity associated with serially moving billions of bits of
data per second. At these data rates, the assumptions associated with digital
signals break down and analog factors demand consideration. The chip
designer who oversimplifies the problem does so at his or her own peril.
Despite this, many chip designers who undertake using HSS cores in their
design do not have a sufficient background to make informed decisions on the
use of HSS features in their application, and to appreciate the potential pitfalls
that result from ignoring the analog nature of the application. Databooks
describe the detailed features of specific HSS devices, but usually assume that
the reader already understands the fundamentals. This is the equivalent of
providing detailed descriptions of the trees, but leaving the reader struggling to
get an overview of the forest.
This text is intended to bridge this gap, and provide the reader with a broad
understanding of HSS device usage. Topics typically taught in a variety of
courses using multiple texts are consolidated in this text to provide sufficient
background for the chip designer that is using HSS devices on his or her chip.
This text may be viewed as consisting of four sections as outlined below.
The first three chapters relate to the features, functions, and design of HSS
devices. Chapter 1 introduces the reader to the basic concepts and the resulting
features and functions typical of HSS devices. Chapter 2 builds upon these
concepts by describing an example of an HSS core, thereby giving the reader
a concrete implementation to use as a framework for topics throughout the
remainder of the text. Although loosely based on the HSS designs offered in
IBM ASIC products, this HSS EX10 is a simplified tutorial example and shares
many features/functions with product offerings from other vendors. Finally,
Chap. 3 introduces interested readers to the architecture and design of HSS
cores using the HSS EX10 as an example.
The next two chapters describe the features and functions of protocol logic
used to implement various network protocol interface standards. Chapter 4
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